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path: root/drivers/cxl/cxlpci.h
AgeCommit message (Expand)AuthorFilesLines
2026-06-29cxl: Support Type2 cxl regs mappingAlejandro Lucero1-12/+0
2026-03-16cxl: Move pci generic code from cxl_pci to core/cxl_pciAlejandro Lucero1-0/+13
2026-02-02cxl/port: Map Port RAS registersTerry Bowman1-0/+5
2026-02-02cxl/port: Move dport RAS setup to dport add timeDan Williams1-3/+4
2026-01-22cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from...Dave Jiang1-0/+16
2026-01-22PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.hTerry Bowman1-53/+0
2025-11-03cxl/port: Remove devm_cxl_port_enumerate_dports()Li Ming1-1/+0
2025-09-18cxl/test: Refactor decoder setup to reduce cxl_test burdenDave Jiang1-2/+0
2025-03-14cxl/pci: Support Global Persistent Flush (GPF)Davidlohr Bueso1-0/+6
2024-05-08PCI/CXL: Move CXL Vendor ID to pci_ids.hDave Jiang1-1/+0
2024-03-12cxl/pci: Get rid of pointer arithmetic reading CDAT tableRobert Richter1-0/+24
2023-12-22cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+13
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron1-0/+1
2023-05-18cxl: Wait Memory_Info_Valid before access memory related infoDave Jiang1-0/+2
2023-04-03cxl/pci: Handle truncated CDAT entriesLukas Wunner1-0/+14
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-1/+2
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang1-1/+2
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso1-0/+6
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-0/+3
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-9/+0
2022-07-19cxl/port: Read CDAT tableIra Weiny1-0/+1
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams1-1/+1
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams1-3/+1
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams1-2/+2
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams1-0/+4
2022-02-08cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky1-0/+13
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-1/+1
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky1-0/+1
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams1-0/+1
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams1-0/+60
generated by cgit (git 2.54.0.dirty) at 2026-09-14 12:36:50 +0000