1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/eswin,pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ESWIN PCIe Root Complex
maintainers:
- Yu Ning <ningyu@eswincomputing.com>
- Senchuan Zhang <zhangsenchuan@eswincomputing.com>
- Yanghui Ou <ouyanghui@eswincomputing.com>
description:
ESWIN SoCs PCIe Root Complex is based on the Synopsys DesignWare PCIe IP.
properties:
compatible:
const: eswin,eic7700-pcie
reg:
maxItems: 3
reg-names:
items:
- const: dbi
- const: config
- const: elbi
ranges:
maxItems: 3
'#interrupt-cells':
const: 1
interrupt-names:
items:
- const: msi
- const: inta
- const: intb
- const: intc
- const: intd
interrupt-map:
maxItems: 4
interrupt-map-mask:
items:
- const: 0
- const: 0
- const: 0
- const: 7
clocks:
maxItems: 4
clock-names:
items:
- const: mstr
- const: dbi
- const: phy_reg
- const: aux
resets:
maxItems: 2
reset-names:
items:
- const: dbi
- const: pwr
patternProperties:
"^pcie@":
type: object
$ref: /schemas/pci/pci-pci-bridge.yaml#
properties:
reg:
maxItems: 1
num-lanes:
maximum: 4
resets:
maxItems: 1
reset-names:
items:
- const: perst
required:
- reg
- ranges
- num-lanes
- resets
- reset-names
unevaluatedProperties: false
required:
- compatible
- reg
- ranges
- interrupts
- interrupt-names
- interrupt-map-mask
- interrupt-map
- '#interrupt-cells'
- clocks
- clock-names
- resets
- reset-names
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
unevaluatedProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie@54000000 {
compatible = "eswin,eic7700-pcie";
reg = <0x0 0x54000000 0x0 0x4000000>,
<0x0 0x40000000 0x0 0x800000>,
<0x0 0x50000000 0x0 0x100000>;
reg-names = "dbi", "config", "elbi";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>,
<0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>,
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>;
bus-range = <0x00 0xff>;
clocks = <&clock 144>,
<&clock 145>,
<&clock 146>,
<&clock 147>;
clock-names = "mstr", "dbi", "phy_reg", "aux";
resets = <&reset 97>,
<&reset 98>;
reset-names = "dbi", "pwr";
interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>;
interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &plic 179>,
<0x0 0x0 0x0 0x2 &plic 180>,
<0x0 0x0 0x0 0x3 &plic 181>,
<0x0 0x0 0x0 0x4 &plic 182>;
device_type = "pci";
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
device_type = "pci";
num-lanes = <4>;
resets = <&reset 99>;
reset-names = "perst";
};
};
};
|
