1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021-2026 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
maintainers:
- Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
description:
This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
interface over Pinctrl device or the output can be routed
to the embedded SerDes for SGMII connectivity.
The DWMAC instances have connected all RX/TX queues interrupts,
enabling load balancing of data traffic across all CPU cores.
properties:
compatible:
oneOf:
- const: nxp,s32g2-dwmac
- items:
- enum:
- nxp,s32g3-dwmac
- nxp,s32r45-dwmac
- const: nxp,s32g2-dwmac
reg:
items:
- description: Main GMAC registers
- description: GMAC PHY mode control register
nxp,phy-sel:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to the GPR syscon node
- description: offset of PHY selection register
description:
This phandle points to the GMAC_0_CTRL_STS register which controls the
GMAC_0 configuration options. The register lets you select the PHY
interface and the PHY mode. It also controls if the FTM_0 or FTM_1
FlexTimer Modules connect to GMAC_0.
interrupts:
minItems: 1
maxItems: 11
interrupt-names:
oneOf:
- items:
- const: macirq
- items:
- const: macirq
- const: tx-queue-0
- const: rx-queue-0
- const: tx-queue-1
- const: rx-queue-1
- const: tx-queue-2
- const: rx-queue-2
- const: tx-queue-3
- const: rx-queue-3
- const: tx-queue-4
- const: rx-queue-4
clocks:
items:
- description: Main GMAC clock
- description: Transmit clock
- description: Receive clock
- description: PTP reference clock
clock-names:
items:
- const: stmmaceth
- const: tx
- const: rx
- const: ptp_ref
required:
- clocks
- clock-names
allOf:
- $ref: snps,dwmac.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 0: tx, rx */
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 1: tx, rx */
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 2: tx, rx */
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 3: tx, rx */
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 4: tx, rx */
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq",
"tx-queue-0", "rx-queue-0",
"tx-queue-1", "rx-queue-1",
"tx-queue-2", "rx-queue-2",
"tx-queue-3", "rx-queue-3",
"tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
};
|
