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| author | Stephen Boyd <sboyd@kernel.org> | 2026-06-13 14:07:48 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2026-06-13 14:07:48 -0700 |
| commit | 834b14a5c4a753a637939008d6c59d4fdc299c7e (patch) | |
| tree | a9da363bfccb6afa8b5b33190e4fc9564ff8d41a /include | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
| parent | a37c75d7b5bb7f3344b0e639b313ac5ace6244ff (diff) | |
Merge tag 'spacemit-clk-for-7.2-1' of ssh://github.com/spacemit-com/linux into clk-spacemit
Pull RISC-V SpacemiT clk driver updates from Yixun Lan:
- Switch SpacemiT PCIe parent clock
- Fix SpacemiT PCIe clock register offset
- Add SpacemiT PCIe DBI clock
* tag 'spacemit-clk-for-7.2-1' of ssh://github.com/spacemit-com/linux:
clk: spacemit: k3: Add PCIe DBI clock
dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
clk: spacemit: k3: Fix PCIe clock register offset
clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/spacemit,k3-clocks.h | 5 | ||||
| -rw-r--r-- | include/soc/spacemit/k3-syscon.h | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h index b22336f3ae40..dfae52547cda 100644 --- a/include/dt-bindings/clock/spacemit,k3-clocks.h +++ b/include/dt-bindings/clock/spacemit,k3-clocks.h @@ -380,6 +380,11 @@ #define CLK_APMU_ISIM_VCLK1 86 #define CLK_APMU_ISIM_VCLK2 87 #define CLK_APMU_ISIM_VCLK3 88 +#define CLK_APMU_PCIE_PORTA_DBI 89 +#define CLK_APMU_PCIE_PORTB_DBI 90 +#define CLK_APMU_PCIE_PORTC_DBI 91 +#define CLK_APMU_PCIE_PORTD_DBI 92 +#define CLK_APMU_PCIE_PORTE_DBI 93 /* DCIU clocks */ #define CLK_DCIU_HDMA 0 diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h index 0299bea065a0..a68255dd641f 100644 --- a/include/soc/spacemit/k3-syscon.h +++ b/include/soc/spacemit/k3-syscon.h @@ -168,8 +168,8 @@ #define APMU_CPU_C2_CLK_CTRL 0x394 #define APMU_CPU_C3_CLK_CTRL 0x208 #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 -#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 -#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 |