Merge tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.18

  - Add initial support for the RZ/T2H (R9A09G077) and RZ/N2H
    (R9A09G087) SoCs and their evaluation boards,
  - Add SPI support for the RZ/V2H SoC,
  - Add DMAC and I3C support for the RZ/G3E SoC,
  - Add I3C support for the RZ/G3S SoCs,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (31 commits)
  arm64: dts: renesas: Minor whitespace cleanup
  arm64: dts: renesas: sparrow-hawk: Set VDDQ18_25_AVB voltage on EVTB1
  arm64: dts: renesas: sparrow-hawk: Invert microSD voltage selector on EVTB1
  arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1 support
  arm64: dts: renesas: r9a09g077: Add pinctrl node
  arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5
  arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
  arm64: dts: renesas: r9a09g047: Add I3C node
  arm64: dts: renesas: r9a08g045: Add I3C node
  arm64: dts: renesas: sparrow-hawk: Update thermal trip points
  arm64: dts: renesas: rzg2: Increase CANFD clock rates
  arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates
  ARM: dts: renesas: porter: Fix CAN pin group
  ARM: dts: renesas: r7s72100: Add boot phase tags
  arm64: dts: renesas: sparrow-hawk: Describe generic SPI NOR support
  arm64: dts: renesas: rzg2lc-smarc: Disable CAN-FD channel0
  arm64: dts: renesas: r9a09g047: Add DMAC nodes
  arm64: dts: renesas: r9a09g057h48-kakip: Fix misplaced article
  arm64: dts: renesas: r9a09g087: Add SDHI nodes
  arm64: dts: renesas: r9a09g077: Add SDHI nodes
  ...

Link: https://lore.kernel.org/r/cover.1756468048.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

3 files changed, 24 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
index 7ecc4f0b235a..0c2ce81a8744 100644
--- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -25,5 +25,6 @@
 #define R9A09G077_CLK_PCLKM		13
 #define R9A09G077_CLK_PCLKL		14
 #define R9A09G077_SDHI_CLKHS		15
+#define R9A09G077_USB_CLK		16
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
index 925e57703925..70ee883f2386 100644
--- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -25,5 +25,6 @@
 #define R9A09G087_CLK_PCLKM		13
 #define R9A09G087_CLK_PCLKL		14
 #define R9A09G087_SDHI_CLKHS		15
+#define R9A09G087_USB_CLK		16
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
new file mode 100644
index 000000000000..f088793f23ee
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/T2H family pinctrl bindings.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
+
+#define RZT2H_PINS_PER_PORT	8
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZT2H_PORT_PINMUX(b, p, f)	((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16))
+
+/* Convert a port and pin label to its global pin index */
+#define RZT2H_GPIO(port, pin)	((port) * RZT2H_PINS_PER_PORT + (pin))
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */