diff options
| author | Yixun Lan <dlan@kernel.org> | 2026-05-11 02:59:10 +0000 |
|---|---|---|
| committer | Yixun Lan <dlan@kernel.org> | 2026-06-02 07:16:59 +0000 |
| commit | 2f20c859a82a291483a8b3f01cbfbb1642782a14 (patch) | |
| tree | 933f2b00a4dc327bde09cfcf768f2997b6450ad5 /include | |
| parent | d8a4cef90b1a4ae9196a5bfba683eb9a0c75acdc (diff) | |
clk: spacemit: k3: Fix PCIe clock register offset
The offset of PCIe Clock CTRL register for port B and C controller was
wrongly swapped, correct it here.
Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-2-c9a5e563bab3@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/soc/spacemit/k3-syscon.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h index 0299bea065a0..a68255dd641f 100644 --- a/include/soc/spacemit/k3-syscon.h +++ b/include/soc/spacemit/k3-syscon.h @@ -168,8 +168,8 @@ #define APMU_CPU_C2_CLK_CTRL 0x394 #define APMU_CPU_C3_CLK_CTRL 0x208 #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 -#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 -#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 |