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path: root/drivers/pci/controller/dwc
AgeCommit message (Expand)AuthorFilesLines
2025-05-28PCI: dwc: ep: Correct PBA offset in .set_msix() callbackNiklas Cassel1-2/+3
2025-05-20PCI: dwc: ep: Fix errno typoNiklas Cassel1-2/+2
2025-05-16PCI: Switch to irq_domain_create_linear()Jiri Slaby (SUSE)5-10/+10
2025-05-15PCI: qcom-ep: Mask PTM_UPDATING interruptManivannan Sadhasivam1-0/+8
2025-05-15PCI: dwc: Add debugfs support for PTM contextManivannan Sadhasivam3-0/+280
2025-05-15PCI: dwc: Pass DWC PCIe mode to dwc_pcie_debugfs_init()Manivannan Sadhasivam4-5/+9
2025-05-13PCI: dwc: Return bool from link up checkHans Zhang18-43/+33
2025-05-10PCI: dwc: ep: Use FIELD_GET() where applicableHans Zhang1-5/+4
2025-05-02PCI: tegra194: Create debugfs directory only when CONFIG_PCIEASPM is enabledHans Zhang1-9/+10
2025-04-28PCI: dwc: Make link training more robust by setting PORT_LOGIC_LINK_WIDTH to ...Wenbin Yao1-4/+1
2025-04-27PCI: dw-rockchip: Fix PHY function call sequence in rockchip_pcie_phy_deinit()Diederik de Haas1-1/+1
2025-04-27PCI: dw-rockchip: Use rockchip_pcie_link_up() to check link up instead of ope...Hans Zhang1-13/+8
2025-04-27PCI: dw-rockchip: Reorganize register and bitfield definitionsHans Zhang1-18/+31
2025-04-27PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG definitionHans Zhang1-1/+0
2025-04-27PCI: imx6: Save and restore the LUT setting during suspend/resume for i.MX95 SoCRichard Zhu1-0/+47
2025-04-27PCI: imx6: Add PLL lock check for i.MX95 SoCRichard Zhu1-0/+29
2025-04-27PCI: imx6: Add workaround for errata ERR051586Richard Zhu1-0/+31
2025-04-27PCI: imx6: Add workaround for errata ERR051624Richard Zhu1-0/+15
2025-04-27PCI: imx6: Toggle the core reset for i.MX95 PCIeRichard Zhu1-0/+42
2025-04-27PCI: imx6: Call dw_pcie_wait_for_link() from start_link() callback only when ...Richard Zhu1-11/+4
2025-04-27PCI: imx6: Skip link up workaround for newer platformsRichard Zhu1-20/+14
2025-04-27PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to dw_pc...Shawn Lin1-6/+1
2025-04-27PCI: dw-rockchip: Enable ASPM L0s capability for both RC and EP modesShawn Lin1-0/+23
2025-04-27PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()Shawn Lin1-3/+1
2025-04-23PCI: qcom: Add support for IPQ5018Nitheesh Sekar1-0/+1
2025-04-23PCI: dwc: Add support for configuring lane equalization presetsKrishna Chaitanya Chundru2-0/+79
2025-04-19PCI: dwc: Update pci->num_lanes to maximum supported link widthKrishna Chaitanya Chundru3-0/+12
2025-04-19PCI: rcar-gen4: set ep BAR4 fixed sizeJerome Brunet1-0/+1
2025-04-07irqdomain: pci: Switch to of_fwnode_handle()Jiri Slaby (SUSE)1-1/+1
2025-03-27Merge branch 'pci/misc'Bjorn Helgaas2-12/+12
2025-03-27Merge branch 'pci/controller/dwc-cpu-addr-fixup'Bjorn Helgaas6-91/+186
2025-03-27Merge branch 'pci/controller/qcom'Bjorn Helgaas1-0/+5
2025-03-27Merge branch 'pci/controller/layerscape'Bjorn Helgaas1-1/+1
2025-03-27Merge branch 'pci/controller/imx6'Bjorn Helgaas1-69/+19
2025-03-27Merge branch 'pci/controller/histb'Bjorn Helgaas1-4/+8
2025-03-27Merge branch 'pci/controller/dwc'Bjorn Helgaas8-0/+868
2025-03-27Merge branch 'pci/controller/amd-mdb'Bjorn Helgaas3-0/+488
2025-03-27Merge branch 'pci/scoped-cleanup'Bjorn Helgaas1-32/+18
2025-03-27Merge branch 'pci/endpoint-test'Bjorn Helgaas1-0/+2
2025-03-27PCI: layerscape: Fix arg_count to syscon_regmap_lookup_by_phandle_args()Ioana Ciornei1-1/+1
2025-03-26PCI: dw-rockchip: Endpoint mode cannot raise INTx interruptsNiklas Cassel1-0/+2
2025-03-24PCI: intel-gw: Remove intel_pcie_cpu_addr()Frank Li1-7/+1
2025-03-24PCI: imx6: Remove imx_pcie_cpu_addr_fixup()Frank Li1-17/+1
2025-03-24PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup()Frank Li3-11/+9
2025-03-24PCI: dwc: ep: Ensure proper iteration over outbound map windowsFrank Li1-1/+1
2025-03-24PCI: dwc: ep: Use devicetree 'reg[addr_space]' to derive CPU -> ATU addr offsetFrank Li1-0/+7
2025-03-24PCI: dwc: ep: Consolidate devicetree handling in dw_pcie_ep_get_resources()Bjorn Helgaas1-15/+29
2025-03-24PCI: dwc: ep: Call epc_create() early in dw_pcie_ep_init()Bjorn Helgaas1-9/+9
2025-03-24PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offsetFrank Li2-0/+7
2025-03-24PCI: dwc: Add dw_pcie_parent_bus_offset() checking and debugFrank Li2-1/+52
generated by cgit (git 2.54.0.dirty) at 2026-09-28 19:30:23 +0000