diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2026-06-13 14:04:36 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2026-06-13 14:04:36 -0700 |
| commit | 0f92f188c8622b7e64d35be99e7ad946a04d5242 (patch) | |
| tree | 96f3aebcb288e8eca06e673b0b21c07c9aff6c66 /include | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
| parent | 7edfb7fb58ee058298e18fde76a6077ef17d19d8 (diff) | |
Merge tag 'v7.2-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Add gate-clocks for i2s outputs on Rockchip rk3588
- Allow compile-tests for the whole clock driver
* tag 'v7.2-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: allow COMPILE_TEST builds
clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO
soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset
clk: rockchip: add helper to register auxiliary GRFs
clk: rockchip: allow grf_type_sys lookup in aux_grf_table
dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/rockchip,rk3588-cru.h | 4 | ||||
| -rw-r--r-- | include/soc/rockchip/rk3588_grf.h | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h index 0c7d3ca2d5bc..7528034cff56 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -734,6 +734,10 @@ #define PCLK_AV1_PRE 719 #define HCLK_SDIO_PRE 720 #define PCLK_VO1GRF 721 +#define I2S0_8CH_MCLKOUT_TO_IO 722 +#define I2S1_8CH_MCLKOUT_TO_IO 723 +#define I2S2_2CH_MCLKOUT_TO_IO 724 +#define I2S3_2CH_MCLKOUT_TO_IO 725 /* scmi-clocks indices */ diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h index 02a7b2432d99..db0092fc66ad 100644 --- a/include/soc/rockchip/rk3588_grf.h +++ b/include/soc/rockchip/rk3588_grf.h @@ -19,4 +19,6 @@ /* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */ #define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0) +#define RK3588_SYSGRF_SOC_CON6 0x0318 + #endif /* __SOC_RK3588_GRF_H */ |