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authorPerry Yuan <perry.yuan@amd.com>2026-02-09 00:42:03 +0800
committerAlex Deucher <alexander.deucher@amd.com>2026-05-11 15:55:55 -0400
commitf9f9fe3a7efba665e1c17fb5186d616c4f0a350f (patch)
tree150a9379105d183432bd27069645d64424bf5868
parent8ce9c73104e34f1fbb8d7f50468e4a62905331f2 (diff)
drm/amdgpu: add PTL enable/query gfx control support for GC 9.4.4
Introduce hardware detection, runtime state tracking and a kgd->ptl_ctrl() callback to enable/disable/query PTL via the PSP performance-monitor interface (commands 0xA0000000/1). The driver now exposes PTL capability to KFD and keeps the software state in sync with the hardware. Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index d0b8fb931720..467a3dbe1bfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2374,11 +2374,43 @@ static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block)
return r;
}
+static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool enable)
+{
+ struct amdgpu_ptl *ptl = &adev->psp.ptl;
+ uint32_t ptl_state = enable ? 1 : 0;
+ uint32_t fmt1, fmt2;
+ int r;
+
+ if (!adev->psp.funcs)
+ return -EOPNOTSUPP;
+
+ if (!ptl->hw_supported) {
+ fmt1 = GFX_FTYPE_I8;
+ fmt2 = GFX_FTYPE_BF16;
+ } else {
+ fmt1 = ptl->fmt1;
+ fmt2 = ptl->fmt2;
+ }
+
+ /* initialize PTL with default formats: GFX_FTYPE_I8 & GFX_FTYPE_BF16 */
+ r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state,
+ &fmt1, &fmt2);
+ if (r)
+ return r;
+
+ ptl->hw_supported = true;
+
+ return 0;
+}
+
static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, num_xcc;
+ if (adev->psp.ptl.hw_supported)
+ gfx_v9_4_3_perf_monitor_ptl_init(adev, false);
+
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
@@ -2553,6 +2585,8 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block)
adev->gfx.ras->enable_watchdog_timer)
adev->gfx.ras->enable_watchdog_timer(adev);
+ gfx_v9_4_3_perf_monitor_ptl_init(adev, true);
+
return 0;
}