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path: root/drivers/cxl/port.c
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2026-06-10cxl/port: update reference to removed CONFIG_PROVE_CXL_LOCKINGEthan Nelson-Moore1-1/+1
2026-02-02Merge branch 'for-7.0/cxl-aer-prep' into cxl-for-nextDave Jiang1-0/+122
2026-02-02cxl/port: Move endpoint component register management to cxl_portDan Williams1-0/+54
2026-02-02cxl/port: Map Port RAS registersTerry Bowman1-0/+6
2026-02-02cxl/port: Move dport RAS setup to dport add timeDan Williams1-0/+12
2026-02-02cxl/port: Move dport probe operations to a driver eventDan Williams1-0/+50
2026-01-05cxl/port: Arrange for always synchronous endpoint attachDan Williams1-0/+40
2025-09-18cxl: Defer dport allocation for switch portsDave Jiang1-8/+3
2025-09-18cxl/test: Refactor decoder setup to reduce cxl_test burdenDave Jiang1-36/+2
2025-06-17sysfs: treewide: switch back to attribute_group::bin_attrsThomas Weißschuh1-1/+1
2025-05-09cxl/region: Move find_cxl_root() to cxl_add_to_region()Robert Richter1-12/+3
2025-02-21cxl/port: Constify 'struct bin_attribute'Thomas Weißschuh1-5/+5
2025-01-02cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()Alejandro Lucero1-1/+1
2024-12-02module: Convert symbol namespace to string literalPeter Zijlstra1-1/+1
2024-11-05sysfs: treewide: constify attribute callback of bin_is_visible()Thomas Weißschuh1-1/+1
2024-10-25cxl/port: Fix CXL port initialization order when the subsystem is built-inDan Williams1-1/+16
2024-09-09cxl/pci: Remove duplicated implementation of waiting for memory_info_validYanfei Xu1-1/+1
2024-07-02cxl: add missing MODULE_DESCRIPTION() macrosJeff Johnson1-0/+1
2024-01-05cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_pr...Dave Jiang1-3/+2
2024-01-05cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang1-1/+3
2023-12-22cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang1-0/+2
2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang1-0/+1
2023-10-27cxl: Add support for reading CXL switch CDAT tableDave Jiang1-0/+3
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-2/+5
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-9/+5
2023-06-25cxl/regs: Remove early capability checks in Component Register setupRobert Richter1-1/+4
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-1/+1
2023-05-18cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang1-6/+0
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams1-5/+9
2023-04-18cxl/port: Scan single-target ports for decodersDan Williams1-5/+13
2023-04-04cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams1-1/+1
2023-04-04cxl/hdm: Skip emulation when driver manages mem_enableDan Williams1-1/+1
2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-5/+10
2023-02-14cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-1/+1
2023-02-14cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-1/+1
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang1-7/+13
2023-02-10cxl/region: Add region autodiscoveryDan Williams1-1/+46
2023-02-10cxl/port: Split endpoint and switch port probeDan Williams1-30/+39
2022-07-19cxl/port: Read CDAT tableIra Weiny1-0/+53
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams1-11/+14
2022-05-19cxl/port: Move endpoint HDM Decoder Capability init to port driverDan Williams1-0/+11
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky1-8/+9
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky1-0/+12
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-4/+4
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky1-0/+63
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