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path: root/arch/x86/kernel/cpu/hygon.c
AgeCommit message (Expand)AuthorFilesLines
2026-07-02x86/hygon: Stop using 32-bit MSR interfacesJuergen Gross1-2/+3
2026-05-06treewide: Explicitly include the x86 CPUID headersAhmed S. Darwish1-0/+1
2025-12-14x86/cpu: Drop vestigial PBE logic in AMD/Hygon/Centaur/CyrixAndrew Cooper1-6/+0
2025-08-18x86/cpu/hygon: Add missing resctrl_cpu_detect() in bsp_init helperTianxiang Peng1-0/+3
2025-05-02x86/msr: Add explicit includes of <asm/msr.h>Xin Li (Intel)1-0/+1
2025-04-10x86/msr: Rename 'rdmsrl_safe()' to 'rdmsrq_safe()'Ingo Molnar1-1/+1
2025-04-10x86/msr: Rename 'rdmsrl()' to 'rdmsrq()'Ingo Molnar1-2/+2
2025-03-04x86/cpu: Simplify TLB entry count storageAhmed S. Darwish1-8/+8
2024-02-15x86/cpu: Use common topology code for HYGONThomas Gleixner1-129/+0
2023-11-13x86/barrier: Do not serialize MSR accesses on AMDBorislav Petkov (AMD)1-0/+3
2023-10-30Merge tag 'x86-core-2023-10-29-v2' of git://git.kernel.org/pub/scm/linux/kern...Linus Torvalds1-19/+19
2023-10-10x86/cpu: Move cpu_l[l2]c_id into topology infoThomas Gleixner1-9/+5
2023-10-10x86/cpu: Move cpu_core_id into topology infoThomas Gleixner1-2/+2
2023-10-10x86/cpu: Move cpu_die_id into topology infoThomas Gleixner1-4/+4
2023-10-10x86/cpu: Move phys_proc_id into topology infoThomas Gleixner1-3/+3
2023-10-10x86/cpu: Encapsulate topology information in cpuinfo_x86Thomas Gleixner1-6/+6
2023-10-10x86/cpu/hygon: Fix the CPU topology evaluation for realPu Wen1-2/+6
2023-09-22x86/cpu: Clear SVM feature if disabled by BIOSPaolo Bonzini1-0/+10
2023-08-09x86/apic: Get rid of hard_smp_processor_id()Thomas Gleixner1-1/+2
2022-12-13Merge tag 'x86_cpu_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds1-1/+1
2022-11-22x86/cpu: Switch to cpu_feature_enabled() for X86_FEATURE_XENPVJuergen Gross1-1/+1
2022-11-15x86/cpu: Restore AMD's DE_CFG MSR after resumeBorislav Petkov1-2/+2
2022-06-27x86/cpu/amd: Add Spectral ChickenPeter Zijlstra1-0/+6
2021-10-21x86/cpu: Fix migration safety with X86_BUG_NULL_SELJane Malalane1-0/+2
2021-06-01perf/x86/rapl: Use CPUID bit on AMD and Hygon partsAndrew Cooper1-0/+4
2021-03-06x86/cpu/hygon: Set __max_die_per_package on HygonPu Wen1-2/+2
2020-12-08x86/cpu/amd: Remove dead code for TSEG region remappingArvind Sankar1-20/+0
2020-11-19x86/CPU/AMD: Save AMD NodeId as cpu_die_idYazen Ghannam1-6/+5
2020-08-06locking/seqlock, headers: Untangle the spaghetti monsterPeter Zijlstra1-0/+1
2019-07-22x86: Remove X86_FEATURE_MFENCE_RDTSCJosh Poimboeuf1-18/+3
2019-03-23x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processorsPu Wen1-0/+5
2018-09-27x86/cpu: Get cache info and setup cache cpumap for Hygon DhyanaPu Wen1-0/+3
2018-09-27x86/cpu: Create Hygon Dhyana architecture support filePu Wen1-0/+405
generated by cgit (git 2.54.0.dirty) at 2026-09-16 01:08:31 +0000