diff options
| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-08-11 23:28:44 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2026-08-31 12:56:49 +0300 |
| commit | 1d79c50e2eeae42b8aad7b5d4d0fe57027174e8a (patch) | |
| tree | ba25c5c2e9a4b1c960cbaea41c4883f69646a25b /scripts/Makefile.thinlto | |
| parent | 0cd42b346d13486f8f31c0846f9f2a9241e191c2 (diff) | |
drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency
DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
be modified.
DDI_CLK_VALFREQ does not have any functional impact on H/w, it
only records the frequency S/w intends to set.
Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
kHz
Fixes: 5ec58d714935 ("drm/i915/lt_phy: Add .enable_clock hook on DDI")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260811175844.2613721-4-suraj.kandpal@intel.com
(cherry picked from commit eaed815ca3483c227e4ec80b86d1b3ce5c2508be)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'scripts/Makefile.thinlto')
0 files changed, 0 insertions, 0 deletions
