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2026-06-17drm/amdxcp: Add more checks to amdxcpLijo Lazar1-6/+12
Add NULL check to ddev argument and guard pdev_num against underflow. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd: add AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU debug maskSamuel Zhang2-3/+10
Kernel parameter `no_console_suspend` is required to capture all hibernation kernel log via serial console. But when the parameter is set, GPU will be resumed in thaw stage. This causes many issues on alinux3 kernel. Fix: add new debug mask `AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU` to replace the check of `console_suspend_enabled` in thaw() callback. User can enable it using `amdgpu.debug_mask=0x800`. Signed-off-by: Samuel Zhang <guoqing.zhang@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: implement per-process MES contextZhu Lingshan3-12/+47
MES process context is a process-level page where process specific context is saved for MES scheduler. However, current user-queue code path assigns fw_obj of a queue to MES process_context_addr when adding the queue to MES. This means every new queue from the same process would replace the previous process context address with that queue's fw_obj address. What's worse is, when user space frees a queue, its fw_obj will be freed as well, causing MES working on a NULL page pointer. This issue leads to inconsistency and crash in the scheduler. This commit allocates a process-level page for MES process contexts for a process other than queue-level Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Add queue reset support on gfx11 dGPUAmber Lin1-0/+5
This patch enables queue reset support to KFD topology for gfx11 dGPUs Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/ras: Estimate RAS reservation when report capacityCe Sun1-1/+25
Add estimate of how much vram we need to reserve for RAS when caculating the total available vram Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17Revert "drm/amdkfd: Add gfx11 queue/pipe reset support to topology"Amber Lin2-4/+0
This reverts commit d04560b5f9c29ff4c1787dad3b491fa115fd07cb. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: remove dead kernel-allocated signal page codeYongqiang Sun2-52/+10
With the KFD_MMAP_TYPE_EVENTS mmap path gone, a kernel-allocated signal page can no longer be exposed to user space, so allocate_signal_page() and the related bookkeeping are dead code. The only remaining way to set up a signal page is kfd_kmap_event_page()/kfd_event_page_set(), where user space allocates the events page as a BO and passes it via the event_page_offset of the create event IOCTL. Remove allocate_signal_page() and require the signal page to be provided by user space. Drop the now unused kfd_signal_page user mapping bookkeeping (user_address/need_to_free_pages) and kfd_event::user_signal_address. Signed-off-by: Yongqiang Sun <Yongqiang.Sun@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/ras: Sync bad page count on EEPROM updateXiang Liu1-0/+3
The rascore EEPROM runtime append path updates the saved bad page count in memory and EEPROM. Keep the SMU bad page count in sync when the EEPROM header is updated so firmware sees the latest count from the runtime threshold path. Notify UPDATE_BAD_PAGE_NUM after computing the rascore UMC bad page count. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Fix mem_type change detection for async flipsMatthew Schwartz1-6/+4
[Why] amdgpu_dm_crtc_mem_type_changed() fetches the "old" and "new" plane state with two drm_atomic_get_plane_state() calls, which both return the new state. It compares a state against itself, so it never detects a mem_type change and never rejects the async flip. On DCN 3.0.1, this shows up as intermittent corruption when a single DCC plane is scanned out with immediate flips under gamescope and its buffer moves between the VRAM carveout and GTT. [How] Use drm_atomic_get_old_plane_state() and drm_atomic_get_new_plane_state() to compare the actual old and new states. These return NULL rather than an error pointer for a plane that is not part of the commit, so the IS_ERR() check becomes a NULL check that skips those planes, such as an unmodified cursor still in the CRTC's plane_mask. Fixes: 4caacd1671b7 ("drm/amd/display: Do not elevate mem_type change to full update") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Matthew Schwartz <matthew.schwartz@linux.dev> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: remove obsolete events page mmap supportYongqiang Sun3-47/+2
The mmap of the events (signal) page from /dev/kfd via KFD_MMAP_TYPE_EVENTS was only needed on APUs using IOMMUv2, which is no longer supported by the kernel mode driver. For dGPUs (and modern APUs) the events page is allocated in user mode and mapped to the kernel through the event_page_offset of the create event IOCTL (kfd_kmap_event_page), so the KFD_MMAP_TYPE_EVENTS mmap path is no longer functional. Remove kfd_event_mmap() and reject KFD_MMAP_TYPE_EVENTS in kfd_mmap, similar to the recent removal of KFD_MMAP_TYPE_RESERVED_MEM. This also removes a way for user space to abuse KFD_MMAP_TYPE_EVENTS of kfd_mmap. Signed-off-by: Yongqiang Sun <Yongqiang.Sun@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add IN_FORMATS_ASYNC support for planesJames Lin1-0/+1
[Why] The DRM core exposes an IN_FORMATS_ASYNC plane property describing the set of format/modifier pairs that are valid for asynchronous (immediate) page flips. amdgpu already advertises async page flip support via mode_config.async_page_flip = true, but never implemented the .format_mod_supported_async plane callback, so the IN_FORMATS_ASYNC property was not created. This inconsistency (advertising async flips while exposing IN_FORMATS but no IN_FORMATS_ASYNC) causes userspace, such as igt-gpu-tools, to emit a repeated warning during plane initialization, which in turn demotes many otherwise passing KMS subtests to a WARN result. [How] Wire up .format_mod_supported_async to the existing amdgpu_dm_plane_format_mod_supported callback so the async format list is populated. amdgpu does not restrict async flips at the format/modifier level: the async flip constraints are enforced at atomic check and commit time and only require a fast update (no change to FB pitch, DCC state, rotation or memory type) between the old and new buffers. Therefore the set of formats/modifiers valid for async flips is identical to the regular IN_FORMATS set, and the same callback can be reused. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: James Lin <PingLei.Lin@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Promote DC to 3.2.386Taimur Hassan1-1/+1
This version brings along the following updates: - Increase dcn42b uclk value. - Add a new interface to set idle opts in clock manager. - Revert dmub_cmd updates for HDMI. - Add utm_qos_model pointer to clk_bw_params. - Remove get_utm_qos_model from soc_and_ip_translator. - Rename hdmi_frl_borrow_mode. - Remove unused project_id from DML2 core instance. - Drop HDMI2_1 guards. - Introduce dc_plane_cm and migrate surface update color path. - Extract backlight code to amdgpu_dm_backlight. - Extract audio code to amdgpu_dm_audio. - Extract DMUB code to amdgpu_dm_dmub. - Move HPD and IRQ handler code to amdgpu_dm_irq. - Extract connector and encoder code to amdgpu_dm_connector. - Fix conflicting types for dc_plane_cm functions. - Add PSR Active VTotal Control capability. - Enable pstate for DCN4 non-emulation builds. - Refactor surface_update_flags to flat struct with helpers. - Add support for HDMI Compliance Automation. - Add KUnit tests for amdgpu_dm and its components. - Set default backlight without ACPI support. - Move backlight macros to backlight header. - Revert use of handle_hpd_irq_helper for HPD RX. - FW Promotion Release 0.1.63.0. Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: [FW Promotion] Release 0.1.63.0Taimur Hassan1-143/+35
[Why & How] Add some CACP command and remove some unused struct and enum. Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17Revert "drm/amd/display: Use handle_hpd_irq_helper for HPD RX"Chenyu Chen1-1/+40
This reverts commit 60597d2cb21990face4ac60bb0f9a642c00ff6d2. Reason for revert: This change is found to cause hang on DP2 link layer compliance 4.2.2.8. Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Tested-by: Mark Broadworth <mark.broadworth@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Move backlight macros to backlight headerAlex Hung3-36/+36
[WHAT] Move AMDGPU_DM_DEFAULT_MIN_BACKLIGHT, AMDGPU_DM_DEFAULT_MAX_BACKLIGHT, AMDGPU_DM_MIN_SPREAD, and AUX_BL_DEFAULT_TRANSITION_TIME_MS from amdgpu_dm_backlight.c to amdgpu_dm_backlight.h so they can be reused by KUnit tests. Update the test file to use these macros instead of hardcoded literal values. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Set default backlight without ACPI supportMario Limonciello1-9/+5
[Why] If BIOS doesn't include ATIF method it will not specify default AC or DC levels. This means that backlight will always start at 0%, which isn't expected behavior. [How] Set default AC and DC level when no valid caps found. Also reduce code duplication for ACPI and non-ACPI cases. Reported-by: Edson Juliano Drosdeck <edson.drosdeck@gmail.com> Closes: https://lore.kernel.org/dri-devel/20260526210048.1162477-1-edson.drosdeck@gmail.com/ Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add more KUnit tests for amdgpu_dm_mst_typesAlex Hung3-49/+491
The following existing functions are also exported for the test module: - needs_dsc_aux_workaround: detect branches needing the DSC AUX workaround - dm_mst_get_pbn_divider: compute the PBN divider from link bandwidth - amdgpu_dm_mst_reset_mst_connector_setting: reset per-connector MST state - retrieve_downstream_port_device: read downstream port presence from DPCD - retrieve_branch_specific_data: read branch OUI from the upstream device Several self-contained pieces of logic are extracted from larger functions into small testable helpers. - dm_dp_aux_transfer_result: AUX return-code to errno mapping - dm_dp_aux_fill_payload_flags: AUX request bit decode - dm_mst_msg_ready_mask: MST sideband ESI mask selection - dm_mst_select_esi_dpcd: DPCD ESI address/length selection Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add more KUnit tests for amdgpu_dm_pp_smuAlex Hung3-103/+889
Expand KUnit coverage of amdgpu_dm_pp_smu.c and extract several pure translation helpers so they can be unit tested in isolation. Extract pure logic into testable helpers: - build_pm_display_cfg() from dm_pp_apply_display_requirements() - build_wm_clock_ranges_soc15() from pp_rv_set_wm_ranges() - cap_clock_levels_to_validation() from dm_pp_get_clock_levels_by_type() - pp_smu_nv_clock_id_to_pp() from pp_nv_set_voltage_by_freq() Tests cover: - pp_to_dc_clock_levels: within-limit copy and count capping - pp_to_dc_clock_levels_with_latency: field copy and count capping - pp_to_dc_clock_levels_with_voltage: field copy and count capping - dm_pp_get_funcs: RV, RV 1.01, NV, RN, and unsupported versions - dm_pp_apply_display_requirements: DPM-disabled early-return path - dm_pp_apply_clock_for_voltage_request: invalid clock type path - build_pm_display_cfg: scalar field scaling and per-display mapping - build_wm_clock_ranges_soc15: DMIF and MCIF range translation - cap_clock_levels_to_validation: engine/memory capping and floor - pp_smu_nv_clock_id_to_pp: valid ids and invalid-id rejection Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_quirksAlex Hung3-0/+106
Add KUnit test file amdgpu_dm_quirks_test.c covering retrieve_dmi_info(). Three test cases are provided: - Verify aux_hpd_discon_quirk is reset to false even when previously true - Verify edp0_on_dp1_quirk is reset to false even when previously true - Verify both quirks remain false on a zero-initialised dm when no DMI match is found (expected in UML/KUnit environment) Register the new test object in the tests/Makefile under CONFIG_DRM_AMD_DC_KUNIT_TEST. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_helpersAlex Hung4-16/+706
Add amdgpu_dm_helpers_test.c with 32 KUnit test cases covering the following functions in amdgpu_dm_helpers.c: - edid_extract_panel_id(): basic extraction with known mfg_id and prod_code; zero inputs produce zero output. - dm_is_freesync_pcon_whitelist(): every entry in the whitelist table returns true; an unknown ID and a zero ID return false. - populate_hdmi_info_from_connector(): scdc_present is copied from hdmi->scdc.supported for both true and false; FRL DSC fields map 10bpc and 12bpc correctly and ignore unknown values. - dm_get_adaptive_sync_support_type(): five cases covering the default non-converter path, HDMI converter without conditions, partial conditions, all conditions met with a whitelist device (FREESYNC_TYPE_PCON_IN_WHITELIST), and all conditions met with a non-whitelisted device. - dm_helpers_is_fullscreen() / dm_helpers_is_hdr_on(): stubs always return false. - get_max_frl_rate(): all six valid lane/rate combinations plus the unknown combination returning 0. - dm_dtn_log_begin()/dm_dtn_log_append_v()/dm_dtn_log_end(): buffer accumulation and NULL-context handling without crashing. - dm_helpers_dp_read_dpcd()/dm_helpers_dp_write_dpcd(): NULL link private data returns false. - dm_helpers_dp_mst_start_top_mgr()/dm_helpers_dp_mst_stop_top_mgr(): NULL link private data and the boot path. - dm_helpers_dp_write_hblank_reduction(): stub returns false. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_servicesAlex Hung3-0/+320
Add amdgpu_dm_services_test.c with KUnit coverage for five functions in amdgpu_dm_services.c: - dm_get_elapse_time_in_ns(): four arithmetic cases covering zero delta, positive delta, ULLONG_MAX span, and unsigned wraparound. - dm_perf_trace_timestamp(): one case verifying the function dereferences ctx->perf_trace safely (the tracepoint is a no-op without an attached probe). - dm_trace_smu_enter(): two cases for the empty stub with NULL ctx and with non-zero parameters. - dm_trace_smu_exit(): three cases for the empty stub covering success, failure, and a non-zero response value. - dm_query_extended_brightness_caps(): four guard-clause cases (NULL ctx, NULL caps, NULL ctx->driver_context, NULL ctx with LCD2) plus two success cases covering the LCD1 slot with luminance data copy and a non-LCD1 display using the second backlight slot with zero data points. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_crtcAlex Hung4-3/+550
Add KUnit coverage for functions in amdgpu_dm_crtc.c: - amdgpu_dm_crtc_modeset_required: verify active+needs_modeset combinations (mode_changed, active_changed, connectors_changed) - amdgpu_dm_crtc_vrr_active_irq: verify all VRR state enum values - amdgpu_dm_crtc_vrr_active: verify all VRR state enum values - amdgpu_dm_is_headless: null adev, no connectors, writeback-only, disconnected display, connected display, and mixed connector cases - amdgpu_dm_crtc_helper_mode_fixup: verify it accepts the mode - amdgpu_dm_crtc_set_vupdate_irq: verify the otg_inst == -1 early return using a DRM mock device - idle_create_workqueue: verify the idle workqueue is allocated and initialized in a disabled, non-running state Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_irqAlex Hung4-3/+955
Add KUnit tests for helper functions, IRQ table management paths, and DRM mock-backed CRTC lookup in amdgpu_dm_irq.c. Tests cover: - amdgpu_dm_hpd_to_dal_irq_source(): all HPD types 1-6, AMDGPU_HPD_NONE, and out-of-range values - are_sinks_equal(): NULL inputs, signal mismatch, EDID length mismatch, EDID data mismatch, identical sinks, zero-length EDID, full-length identical EDID, and a single trailing-byte difference - dmub_notification_type_str(): notification type mappings that are always built, plus the unknown/default case - amdgpu_dm_irq_init(): low/high handler list initialization - amdgpu_dm_irq_register_interrupt(): NULL input rejection, invalid context/source rejection, low/high handler insertion, multiple handlers on one source, and the same handler registered in both low and high contexts - amdgpu_dm_irq_unregister_interrupt(): invalid source and NULL handler rejection, removal of registered low/high handlers, and the handler-not-found path - amdgpu_dm_irq_fini(): cleanup of registered low/high handlers and the empty-table case - amdgpu_dm_get_crtc_by_otg_inst(): DRM mock CRTC list match, no-match, and empty-list paths Assisted-by: Copilot:Claude-Opus-4 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_connectorAlex Hung4-7/+2184
Add KUnit tests for helper functions in amdgpu_dm_connector.c, including both pure helper tests and DRM mock-based tests. Tests cover: - get_subconnector_type(): all dongle types and unknown default - get_output_content_type(): all content type mappings and unknown default - adjust_colour_depth_from_display_info(): depth reduction from 12bpc to 10bpc, 16bpc no-fallback, YCbCr420 clock halving, and no-fit rejection - get_output_color_space(): RGB full/limited, YCbCr default 709/601, BT601/709 with Y_ONLY, OPRGB, BT2020 RGB/YCC paths - convert_dc_color_depth_into_bpc(): all depths and undefined default - convert_color_depth_from_display_info(): non-Y420 bpc values, Y420 default/10/12/16bpc, requested odd bpc rounding, unsupported bpc, and requested_bpc capping - to_drm_connector_type(): HDMI, eDP, LVDS, RGB, DP/MST, DVI single and dual link DVII/DVID, virtual, and unknown - is_duplicate_mode(): empty list, match, no-match, and same-size different-clock cases - amdgpu_dm_get_encoder_crtc_mask(): 1-6 CRTCs and default - get_aspect_ratio(): all HDMI picture aspect ratios - decide_crtc_timing_for_drm_display_mode(): scale enabled, matching mode, no copy, and no crtc_clock cases - amdgpu_dm_connector_funcs_reset(): default fields, eDP ABM level set, and eDP ABM disabled - amdgpu_dm_connector_atomic_duplicate_state(): field copy verification - amdgpu_dm_fill_hdr_info_packet(): null metadata early return and output zeroing - amdgpu_dm_connector_atomic_set_property(): scaling center/aspect/ fullscreen/none/unchanged, underscan hborder/vborder/enable, abm sysfs control/level off/level value, and unknown property -EINVAL - amdgpu_dm_connector_atomic_get_property(): scaling center/aspect/ full/off, underscan borders, abm sysfs allowed/level/disabled, and unknown property -EINVAL - amdgpu_dm_get_highest_refresh_rate_mode(): null writeback, cached base mode, and preferred mode selection - amdgpu_dm_is_freesync_video_mode(): null mode, match, and no-match cases Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_dmubAlex Hung3-0/+610
Add KUnit tests for amdgpu_dm_dmub.c covering the following functions: - dm_register_dmub_notify_callback(): NULL callback rejection, out-of-range type, valid registration with offload flag - dm_dmub_aux_setconfig_callback(): copy and complete on AUX reply, non-AUX skip, NULL dm_notify, SET_CONFIG reply - dm_dmub_aux_fused_io_callback(): copy reply and complete, max ddc_line boundary - dm_get_default_ips_mode(): IPS mode per DCN version (3.5, 3.5.1, 3.6, 4.2), disabled for older ASICs, default enabled for unhandled newer ASICs - dm_dmub_hw_init(): early returns for no dmub_srv, no fb_info, no firmware - dm_dmub_hw_resume(): no-op when dmub_srv is NULL - dm_dmub_sw_init(): returns 0 for unsupported ASIC - dm_init_microcode(): returns 0 for unsupported ASIC Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_audioAlex Hung4-3/+527
Add KUnit tests for amdgpu_dm_audio.c. Tests cover: - amdgpu_dm_audio_init(): early exit when audio is disabled - amdgpu_dm_audio_fini(): early exit when audio is not enabled - fill_audio_info(): manufacturer and product ID propagation, display name copy, speaker allocation flags, CEA revision gating of audio mode copying (including the zero-mode case), and latency field propagation - amdgpu_dm_audio_component_bind()/unbind(): component ops, device, and audio_component pointer are wired up on bind and cleared on unbind - amdgpu_dm_audio_eld_notify(): callback is forwarded with the correct port and audio pointer, and the no-op guard paths for a missing component, audio_ops, or pin_eld_notify callback Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_backlightAlex Hung4-9/+1210
Add KUnit tests for the backlight helpers in amdgpu_dm_backlight.c. Tests cover: - amdgpu_dm_update_backlight_caps(): short-circuit on populated caps and default value assignment - get_brightness_range(): NULL, PWM-only, and AUX backlight paths - convert_brightness_to_user(): minimum clamp, maximum passthrough, and mid-range rescaling - convert_brightness_from_user(): linear rescaling, AUX path, and custom-curve mapping - convert_custom_brightness(): exact match, below-first, interpolation, above-last, single data point, zero lower luminance, and the debug-mask and no-data-point guards - amdgpu_dm_update_connector_ext_caps(): negative bl_idx and non-eDP early returns, OLED defaults, luminance range copy, and the amdgpu_backlight force-AUX/force-PWM overrides - amdgpu_dm_should_create_sysfs(): forced ABM, non-eDP, missing backlight index, and AUX vs PWM backlight - amdgpu_dm_setup_backlight_device(): non-eDP/LVDS skip, disconnected link skip, eDP-count limit, and the successful eDP setup path Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dmAlex Hung5-15/+979
Add KUnit tests for pure helper functions in amdgpu_dm.c. Tests cover: - dm_plane_layer_index_cmp(): equal, ascending, and descending layer_index ordering - fill_plane_color_attributes(): RGB plus BT601/BT709/BT2020 full- and limited-range YCbCr, and invalid encoding - modereset_required(): active vs inactive stream states with and without a mode change - dm_get_oriented_plane_size(): 0/90/180/270 degree rotations - dm_get_plane_scale(): identity, rotated identity, and division-by-zero guard - is_scaling_state_different(): identical state, scaling mode change, and underscan enable/border changes - is_timing_unchanged_for_freesync(): NULL args, identical modes, VRR vtotal/vsync shift, and pixel clock change - set_freesync_fixed_config(): fixed refresh-rate computation - is_dc_timing_adjust_needed(): pending hw adjust, VRR active-fixed, VRR active-state toggle, and steady state - set_multisync_trigger_params(): disabled trigger and rising/falling edge selection by vsync polarity - set_master_stream(): highest refresh-rate selection and the default-to-first-stream case Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add Support for HDMI Compliance AutomationFangzhi Zuo4-1/+80
Add support to get DUT trained at FRL link rate when working with Teledyne M41h compliance automation. Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Refactor surface_update_flags to flat struct with helpersRafal Ostrowski14-233/+343
[Why] The union surface_update_flags type uses a union with a raw uint32_t member to allow bulk clear/set/test operations on the bitfield. This couples the struct layout to a specific integer width, breaks when the number of flag bits exceeds 32, and scatters raw-access patterns across many call sites. Replacing the union with a plain struct and adding explicit helper functions makes the intent clearer and prepares the code for future flag-set expansion. [How] Rename union surface_update_flags to struct pipe_update_bits and remove the union wrapper, the .bits sub-struct, and the .raw member. Add inline helpers in dc.h: surface_update_flags_clear(), surface_update_flags_set_full(), and surface_update_flags_is_any_set() that operate on the new struct via memset/memcmp. Add stream_update_flags_clear() and stream_update_flags_set_full() in dc_stream.h for the stream update flags union. Update all callers: change the type name, replace .bits.field with .field, replace .raw = 0 with the clear helper, replace .raw = 0xFFFFFFFF with the set_full helper, and replace .raw boolean tests with is_any_set. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Enable pstate for DCN4 non-emulation buildsGabe Teeger1-1/+1
[Why] Pstate was disabled during bring-up to avoid interference. Now that bring-up is complete it can be enabled for non-emulation builds. [How] Set pstate_enabled to true in debug_defaults_drv for non-emulation DCN4 builds. Reviewed-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add PSR Active VTotal Control capabilityRobin Chen3-1/+7
[WHY] The PSRSU-RC capability should be populated in DC during edp detection. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract connector and encoder code to amdgpu_dm_connectorAlex Hung7-3646/+3820
Move connector lifecycle functions (init, detect, mode validation, property handling, EDID parsing, hotplug processing) and encoder functions (init, destroy, atomic_check, helper_funcs) from amdgpu_dm.c to amdgpu_dm_connector.c. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Move HPD and IRQ handler code to amdgpu_dm_irqAlex Hung4-1500/+1538
Move HPD handling (workqueue creation, debounce, handler registration) and IRQ handler callbacks (vblank, pflip, vupdate, vline0, outbox) from amdgpu_dm.c into the existing amdgpu_dm_irq.c. This keeps all IRQ-related code together rather than creating additional files. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract DMUB code to amdgpu_dm_dmubAlex Hung4-920/+1002
Move DMUB-related functions and firmware defines from amdgpu_dm.c into new amdgpu_dm_dmub.c and amdgpu_dm_dmub.h files to reduce the size of amdgpu_dm.c and improve code organization. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract audio code to amdgpu_dm_audioAlex Hung4-267/+350
Move audio component, init/fini, ELD notification, fill_audio_info, and commit_audio functions from amdgpu_dm.c into a dedicated amdgpu_dm_audio.c file with its own header. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract backlight code to amdgpu_dm_backlightAlex Hung6-619/+710
Move backlight-related functions from amdgpu_dm.c into a new amdgpu_dm_backlight.c file to improve code organization and reduce the size of the monolithic amdgpu_dm.c. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Introduce dc_plane_cm and migrate surface update color pathRafal Ostrowski18-429/+587
[Why] Begin convergence with upstream Color Manager refactor (fda768acb2a1 "drm/amd/display: Sync dcn42 with DC 3.2.373") by consolidating fragmented per-plane CM state (shaper, 3DLUT, blend, CM2) into a single dc_plane_cm structure shared by dc_plane_state and dc_surface_update. Legacy fields are gated behind TRIM_CM2 so that it keeps compatibility with other repositories. [How] Refactored to use newer structures. No functional behavior change intended. Under !TRIM_CM2 the legacy fields are still populated for compatibility with other repositories. v2: squash in conflicting types fix Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove unused project_id from DML2 core instanceWenjing Liu3-5/+0
[Why] The project_id field stored in dml2_core_instance and related context structs was not consumed after initial setup and represents unnecessary coupling between the core layer and project-specific identifiers. [How] - Remove project_id field from dml2_core_instance - Remove the corresponding assignment in dml2_core_create Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove get_utm_qos_model from soc_and_ip_translatorWenjing Liu1-14/+0
[Why] The QoS model is now populated directly in clock manager from firmware data. The translator function pointer is no longer needed. [How] - Remove get_utm_qos_model function pointer from soc_and_ip_translator_funcs - Remove associated forward declarations from soc_and_ip_translator.h Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add utm_qos_model pointer to clk_bw_paramsWenjing Liu1-0/+2
[Why] Add support for passing QoS model data from clock manager to bandwidth calculation consumers. [How] - Add forward declaration and const pointer for utm_qos_model in clk_bw_params Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add a new interface to set idle opts in clock managerNicholas Kazlauskas1-0/+2
[Why & How] For future use in migrating the idle optimizations message to PMFW to DC core. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Increase dcn42b uclk valueGabe Teeger1-1/+1
Increase uclk value in order to enable UHBR20. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/ras: Add address sanity check for unirasCe Sun7-7/+68
Add address sanity check for uniras Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: correct reservation fence slots for userq per-vm BOs evictionPrike Liang1-1/+2
It fixes both the move overflow and the eviction fence add for evicting these per-vm BOs. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: add sdma queue counter for gfxv9.4.3Eric Huang6-8/+107
since gfx 9.4.3 HW is calculating accumulated activity counter per-queue in register sdmax_rlcx_utilization_hi/lo, CPFW adds it in sdma MQD for save/restore, KFD will read it from there. gfx 9.4.2 will still keep the way to read from memory at rptr+8. v2: read dynamic counter directly from utilization register v3: add CPFW supported version check (Harish) Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Add gfx11 queue/pipe reset support to topologyAmber Lin2-0/+4
Add gfx11 queue/pipe reset support to KFD topology Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Fix reset event signalAmber Lin1-1/+5
During the KFD/KCQ coordination rework, bad queues not requiring reset were combined into the rework and generated wrong reset signals to the process. Fix it by adding the reset check. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: Don't use UTS_RELEASE directlyUwe Kleine-König (The Capable Hub)1-2/+2
UTS_RELEASE evaluates to a static string and changes quite easily (e.g. uncommitted changes in the source tree or new commits). So when checking if a patch introduces changes to the resulting binary each usage of UTS_RELEASE is source of annoyance. Instead of using UTS_RELEASE directly use init_utsname()->release which evaluates to the same string but with that a change of UTS_RELEASE doesn't affect amdgpu_dev_coredump.o. Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20260428144704.1114562-2-u.kleine-koenig@baylibre.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/gfx: fix cleaner shader IB buffer overflowAsad Kamal1-5/+5
The cleaner shader sysfs path allocates a 16-dword (64 byte) IB but incorrectly fills (align_mask + 1) dwords. On GFX rings align_mask is 0xff, so the loop wrote 256 dwords into a 64-byte buffer, causing a kernel page fault. The IB only needs to be a minimal NOP shell to schedule the job; the cleaner shader itself is emitted on the ring via emit_cleaner_shader(). Fill 16 dwords to match the allocation. v2: Use ib_size_dw variable (Lijo) Fixes: d361ad5d2fc0 ("drm/amdgpu: Add sysfs interface for running cleaner shader") Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.54.0.dirty) at 2026-10-01 00:59:56 +0000