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2026-06-17drm/amdgpu/ras: Add flag to make VBIOS read optionalCe Sun1-1/+1
Add flag to make VBIOS read optional Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: allocate lockdep mutex on the heap to fix stack overflowPrike Liang1-50/+53
Replace the stack-allocated amdgpu_lockdep mutex with a heap allocation via kmalloc to fix a stack overflow caused by the large struct size. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/ras: added RAS EEPROM device support checkCe Sun1-1/+17
Added RAS EEPROM device support check Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/ras: Parse all deferred errors with UMC aca handleCe Sun1-7/+6
We should only increase the deferred errors in UMC block Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Promote DC to 3.2.385Taimur Hassan1-1/+1
Summary: * Display connectivity & HPD: - Retry link detection on resume, boot, and hotplug - Refactor HPD RX to use handle_hpd_irq_helper with detect reason - Always create delayed HPD work queue - Restore periodic detection for DCN35 * DCN42B support: - Fix DCN42B version detection - Add DCN42B to dml21_translation_helper * KUnit testing infrastructure: - Add KUnit tests for amdgpu_dm_pp_smu, amdgpu_dm_mst_types, and writeback connector - Extract HDCP and DPRX CRC transition helpers for KUnit - Export symbols for KUnit test modules - Enable warnings as errors for KUnit tests * Fixes & cleanups: - Fix compressed buffer config routine waiting time - Fix incorrect logic in CRC source handling - Fix writeback format loop and variable init - Fix max dispclk_khz/dppclk_khz double 1000 - Remove duplicate pp_rn_set_wm_ranges - Remove dead code in dm_dp_mst_get_modes - Remove redundant code in amdgpu_dm_replay - Skip PHY SSC reduction on some 8K panels - Temp disable repeater FGCG as workaround - Deprecate DMUB register offload functionality - TEST_HARNESS FSN could be 0 * Firmware: - DMUB FW promotion to 0.1.62.0 Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: fix compressed buffer config routine waiting timeAntonio Quartulli1-4/+4
Replace the four open-coded REG_WAIT calls with calls to dcn31_wait_for_det_apply() so the compressed buffer (compbuf) sizing path waits long enough for the DET size update to take effect, and the wait timing stays consistent across the driver. No functional change beyond the corrected timeout. Signed-off-by: Antonio Quartulli <antonio@mandelbit.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Use handle_hpd_irq_helper for HPD RXTimur Kristóf1-40/+1
Remove duplicated code and just call handle_hpd_irq_helper with the appropriate detect reason. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Fix SMI event PID reporting for containersAndrew Martin5-56/+77
SMI events were reporting incorrect PIDs in containerized environments, causing test failures where container processes expected to see their namespace-local PIDs but instead received global host PIDs. The issue had two root causes: 1. Event functions were called from kernel context (page fault handlers, migration workers) where 'current' refers to the kernel worker thread, not the userspace GPU process that triggered the event. 2. PID conversion used task_tgid_vnr() which returns the PID in the caller's namespace (init namespace for kernel threads), not the task's own namespace. This patch updates the SMI event interface: - Change 8 event function signatures to accept task_struct pointer instead of pid_t, allowing proper namespace-aware PID conversion - Convert PIDs using task_tgid_nr_ns(task, task_active_pid_ns(task)) which returns the PID as the process sees it via getpid() - Update 10 call sites to pass p->lead_thread (the GPU process) instead of p->lead_thread->pid or current (kernel worker) This ensures SMI events report container-local PIDs, which is critical for containerized GPU workloads to correctly correlate events with their processes. Tested-by: Andrew Martin <andmarti@amd.com> Assisted-by: Claude:Sonnet 4-5 Signed-off-by: Andrew Martin <andrew.martin@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add detect reason to handle_hpd_irq_helperTimur Kristóf1-7/+11
This makes it possible to reuse the function for other purposes in the next few commits, such as HPD RX. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/gfx: defer per-queue helper_end until after MES resumeJesse Zhang2-8/+65
amdgpu_gfx_reset_mes_compute() runs amdgpu_mes_suspend(adev, 0) to quiesce all gangs, resets the offending queue(s), then resumes. The existing amdgpu_gfx_mes_reset_queue() called amdgpu_ring_reset_helper_end() right after unmap/restore/map of the reset queue, which re-emits backed-up commands and rings the doorbell. That doorbell hits a still-suspended CP: on the subsequent resume the queue partially wedges -- the first new IB after the reset may execute but later submissions stall, which surfaces as repeated timeouts on the same ring under concurrent workloads. Split out amdgpu_gfx_mes_reset_queue_start() (backup + MES reset + unmap/restore/map only) and defer helper_end. amdgpu_gfx_reset_mes_compute() collects the (ring, fence) pair for every queue it resets and runs helper_end on each after amdgpu_mes_resume(), so the re-emit doorbells land on a running CP. amdgpu_gfx_reset_mes_kcq() now reports the matched ring/fence back to the caller for the same reason. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_pp_smuAlex Hung4-2/+265
[WHAT] Add KUnit tests for two functions in amdgpu_dm_pp_smu.c: get_default_clock_levels and dc_to_pp_clock_type. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove duplicate pp_rn_set_wm_rangesAlex Hung1-12/+1
[WHAT] Remove pp_rn_set_wm_ranges and reuse the identical pp_nv_set_wm_ranges for the DCN_VERSION_2_1 case instead. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Restore periodic detection for DCN35Ivan Lipski3-4/+2
[Why&How] Periodic detection callbacks from DCN35 was removed for higher IPS residency causing some displays to fail to recover after DPMS sleep. The monitors bounces HPD ~1.2s after link training, and without periodic detection the system enters IPS with no mechanism to wake and rediscover the display. Restore the periodic detection calls in dcn35_clk_mgr for now. It should be replaced with a proper IPS-aware solution long term using DMUB. Also remove it from dcn31 and dcn314_clk_mgr.c since they do not have IPS, thus should not affect them. Fixes: 3f6c060846be ("drm/amd/display: Remove periodic detection callbacks from dcn35+") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5318 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract HDCP testable helpers for KUnitAlex Hung3-54/+370
[WHAT] Extract hdcp_get_content_protection_from_status() and hdcp_get_link_display_adjustments() from event_property_update() and hdcp_update_display() so the pure decision logic can be KUnit-tested. Also update function comments to kernel-doc formats. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract DPRX CRC transition helpers for KUnit testingAlex Hung3-17/+203
Extract three pure predicate functions from amdgpu_dm_crtc_set_crc_source(): - dm_need_dp_aux - dm_crc_source_should_start_dprx - dm_crc_source_should_stop_dprx Refactor set_crc_source() to use these helpers, replacing the nested if/else if structure with flat, mutually-exclusive branches driven by the new predicates. Add KUnit test cases covering all relevant source combinations for each helper, including the regression case where DPRX→NONE must trigger drm_dp_stop_crc(). Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Fix incorrect logic in CRC source handlingAlex Hung1-5/+5
[WHAT] Fix three issues amdgpu_dm_crc.c: - Use cur_crc_src instead of source when deciding whether to call drm_dp_stop_crc() in the disable path of set_crc_source(). When disabling CRC, source is always NONE so dm_is_crc_source_dprx(source) was always false, meaning drm_dp_stop_crc() was never called when stopping a DPRX CRC source. Use cur_crc_src to check what was previously active instead. - Replace fragile 'source < 0' comparisons in verify_crc_source() and set_crc_source() with AMDGPU_DM_PIPE_CRC_SOURCE_INVALID. and avoiding signed/unsigned enum comparison concerns. - Remove redundant NULL initializations for drm_dev and acrtc in handle_crc_irq(). Both variables are unconditionally assigned right after. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_mst_typesAlex Hung4-0/+133
[WHAT] Add KUnit test coverage for needs_dsc_aux_workaround() in amdgpu_dm_mst_types.c. Tests verify the function correctly identifies links requiring the DSC AUX workaround based on branch device ID, DPCD revision, and sink count. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove dead code in dm_dp_mst_get_modesAlex Hung1-14/+9
[WHAT] Remove unreachable null check on aconnector after container_of, and redundant dc_sink checks where dc_sink is guaranteed non-NULL after earlier null-check with early return. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Enable warnings as errors for KUnit testsAlex Hung1-0/+3
[WHAT] Add CONFIG_WERROR=y to .kunitconfig to treat compiler warnings as errors during KUnit builds, ensuring warnings are caught early. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: remove redundant code in amdgpu_dm_replayAlex Hung1-5/+2
[WHAT] In amdgpu_dm_link_setup_replay(), nom_coasting_vtotal was used only once immediately after in set_replay_coasting_vtotal(). Inline the value directly to remove the no-op alias. In amdgpu_dm_set_replay_caps(), replace link->ctx->dc->debug with dc->debug since dc is already assigned as link->ctx->dc, eliminating a redundant pointer round-trip. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: fix max dispclk_khz/dppclk_khz double 1000Charlene Liu1-4/+4
[why] Fix regresson caused by double roundup and index out of range Reviewed-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for writeback connectorAlex Hung4-2/+355
[WHAT] Add KUnit tests for amdgpu_dm_wb_encoder_atomic_check() and amdgpu_dm_wb_connector_get_modes(). Tests cover null job, null fb, size mismatch, format validation, and mode count bounds using DRM KUnit mock devices. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Fix writeback format loop and variable initAlex Hung1-3/+5
[WHAT] 1. Use ARRAY_SIZE() instead of manual sizeof division for the format array iteration. Add a break statement to exit the loop early once a matching format is found. 2. Remove redundant zero initialization of res since all paths assign before use. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Temp disable repeater FGCG as workaroundOvidiu Bunea5-2/+21
[why & how] There is an issue that is seemingly limited to DCN42 where systems with IOMMU enabled will hang during reboot stress testing. The hang happens shortly after DCN PG exit happens and HUBP is programmed for the first flip, but before the first surface address is latched. Testing has shown that disabling DCCG_GLOBAL_FGCG_REP_DIS, HUBP_FGCG_REP_DIS, and DCFCLK_GATE_DIS can mask this issue. Disable FGCG for these three repeater bits to avoid issue while debug is on-going. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Deprecate DMUB register offload functionalityAustin Zheng20-330/+0
[Why] The DMUB register offload feature should no longer be used. This was originally a debug feature for DCN21. No longer applicable to the DMUB programming model. [How] Remove DMUB register offload infrastructure including helper functions, structures, debug options, and register sequence macros. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: TEST_HARNESS FSN could be 0ChunTao Tso1-5/+4
The frame skipping number could be 0 if needed. Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: ChunTao Tso <ChunTao.Tso@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Skip PHY SSC reduction on some 8K panelsRoman Li1-3/+10
[Why] Some 8K displays cannot tolerate the reduced phy ssc value at high link utilization and show corruption or black screen. [How] Add an EDID panel-id quirk to utilize existing skip_phy_ssc_reduction flag. To pass the link into the quirk handler, change the signature of apply_edid_quirks() to take link as an argument. The dev local in dm_helpers_parse_edid_caps() becomes unused and is removed. Fixes: 5fa62c87cffd ("drm/amd/display: Add option to disable PHY SSC reduction on transmitter enable") Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Extend MQDs in HBM to gfx944Kent Russell1-0/+1
This has proven stable and performant on gfx943 and gfx950, so extend it to gfx944 as well Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Extend MQDs in HBM to gfx942Kent Russell1-0/+1
This has proven stable and performant on gfx943 and gfx950, so extend it to the Aldebaran/gfx942 series Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: remove spurious line in amdgpu_ring_find_guilty_fence()Alex Deucher1-1/+0
Copy-paste error. Fixes: 36ed61b1c01a ("drm/amdgpu/fence: add helper to extract the guilty fence") Reviewed-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: skip already suspended IP blocks in ip_suspend_phase2Yunxiang Li1-1/+1
The GPU reload test (S3 / mode1 reset / module reload) triggers a WARN_ON in amdgpu_irq_put() on gfx10 when unloading amdgpu: WARNING: CPU: 0 PID: 2314 at amd/amdgpu/amdgpu_irq.c:676 amdgpu_irq_put+0xc3/0xe0 [amdgpu] Call Trace: gfx_v10_0_hw_fini+0x41/0x150 [amdgpu] amdgpu_ip_block_hw_fini+0x29/0xc0 [amdgpu] amdgpu_device_fini_hw+0x315/0x610 [amdgpu] amdgpu_driver_unload_kms+0x7c/0x90 [amdgpu] amdgpu_pci_remove+0x51/0x90 [amdgpu] amdgpu_device_ip_resume_phase2() skips IP blocks whose status.hw is already set, but amdgpu_device_ip_suspend_phase2() never had the matching guard, so a block can be suspended twice (e.g. a reset or recovery issued while the device is already suspended). The second suspend runs hw_fini again, which now releases the gfx fault IRQs unconditionally, dropping a refcount that is already zero and tripping the WARN_ON in amdgpu_irq_put(). The fault/EOP IRQ get/put were balanced through late_init/hw_fini before, which masked the double-suspend; moving the get into hw_init made the suspend/resume asymmetry visible as an IRQ refcount underflow. Honor status.hw in ip_suspend_phase2() so suspend mirrors resume and a block is only torn down once. Fixes: 9117d8be850b ("drm/amdgpu/gfx: move fault and EOP IRQ get/put to hw_init/hw_fini") Fixes: 482f0e538580 ("drm/amdgpu: fix double ucode load by PSP(v3)") Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Move mqd_on_vram out of v9 mqd managerKent Russell3-14/+16
This will allow it to be used outside of gfx9 Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Properly acquire queue buffers in CRIU restoreDavid Francis1-2/+10
When kfd_queue_acquire_buffers() was split off from set_queue_properties_from_user(), set_queue_properties_from_criu() was missed. Thus, set_queue_properties_from_criu() is not filling out the buffer fields of queue_properties, which can come up when subsequent code expects them to be non-null. Add the proper call to kfd_queue_acquire_buffers(), and also use the right cast types in set_queue_properties_from_criu() (which were missed at the same time) Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/pm: re-enable MC access after PrepareMp1ForUnload on SMU V15 APUsShubhankar Milind Sardeshpande1-1/+6
During smu_v15_0_0_system_features_control(), the driver sends a PrepareMp1ForUnload message to PMFW. PMFW then performs nBIF and SYSHUB function-level resets (FLR), disabling PCIe CFG space reset, which clears the framebuffer enable bit to zero and disables MC (memory controller) access from the host. Re-enable MC access via the nbio mc_access_enable callback right after PrepareMp1ForUnload completes in smu_v15_0_0_system_features_control(). Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Signed-off-by: Suresh Guttula <Suresh.Guttula@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/vcn4.0.5: enable secure submission on unified ringJeevana Muthyala1-4/+2
Set secure_submission_supported = true for the VCN unified ring funcs in vcn_v4_0_5.c so secure IBs are allowed on the unifiedring. Without this, protected decode submissions are blocked by the common IB gate and can fail playback for secure content. For vcn_v4_0_5.c (fixed STX VCN version), secure submission is enabled directly in the ring funcs definition. This change only advertises existing hardware/firmware capability; non-secure decode paths are unaffected. Signed-off-by: Jeevana Muthyala <jmuthyal@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/vcn4.0: enable secure submission on unified ringJeevana Muthyala1-5/+40
Set secure_submission_supported = true for the VCN unified ring funcs in vcn_v4_0.c so secure IBs are allowed on the unified ring. Without this, protected decode submissions are blocked by the common IB gate and can fail playback for secure content. For vcn_v4_0.c, the secure ring funcs are selected for the secure-capable IP version. This change only advertises existing hardware/firmware capability; non-secure decode paths are unaffected. Signed-off-by: Jeevana Muthyala <jmuthyal@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/pm: sleep on PMFW EEPROM busy in bad page count queryCandice Li1-1/+1
Use usleep_range() instead of mdelay() to match the behavior of ras_fw_get_badpage_count() in rascore path. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/ras: sleep on PMFW EEPROM busy in bad page count queryCandice Li1-1/+1
Use usleep_range() instead of mdelay() when ras_fw_get_badpage_count() retries on -EBUSY so the driver yields the CPU while waiting for PMFW EEPROM to become ready. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: initialize iter.start in amdgpu_devcoredump_formatQiang Yu1-0/+1
This fixes read /sys/class/drm/cardN/device/devcoredump/data return empty content sometimes. amdgpu_devcoredump_format() leaves struct drm_print_iterator's .start field uninitialized on the stack before passing it to drm_coredump_printer(). __drm_puts_coredump() compares the running .offset against .start to decide whether to skip or copy each chunk: if (iterator->offset < iterator->start) { if (iterator->offset + len <= iterator->start) { iterator->offset += len; return; } ... } Fixes: 4bbba79a7f1d ("drm/amdgpu: move devcoredump generation to a worker") Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Avoid double-unpin of DOORBELL/MMIO BOs on freeYunxiang Li1-7/+9
amdgpu_amdkfd_gpuvm_free_memory_of_gpu() unpinned DOORBELL and MMIO remap BOs (which are pinned at allocation time) before checking whether the BO is still mapped to the GPU. When the BO is still mapped, the function returns -EBUSY and leaves the BO alive, but it has already been unpinned. The BO is then unpinned again when it is finally freed during process teardown, triggering a ttm_bo_unpin() underflow warning: WARNING: CPU: 18 PID: 15066 at ttm/ttm_bo.c:650 amdttm_bo_unpin+0x6d/0x80 [amdttm] Workqueue: kfd_process_wq kfd_process_wq_release [amdgpu] RIP: 0010:amdttm_bo_unpin+0x6d/0x80 [amdttm] Call Trace: amdgpu_bo_unpin+0x1a/0x90 [amdgpu] amdgpu_amdkfd_gpuvm_unpin_bo+0x31/0xb0 [amdgpu] amdgpu_amdkfd_gpuvm_free_memory_of_gpu+0x3bf/0x460 [amdgpu] kfd_process_free_outstanding_kfd_bos+0xd4/0x170 [amdgpu] kfd_process_wq_release+0x109/0x1b0 [amdgpu] process_one_work+0x1e2/0x3b0 worker_thread+0x50/0x3a0 kthread+0xdd/0x100 ret_from_fork+0x29/0x50 Move the unpin after the mapped_to_gpu_memory check so it only happens once we are committed to freeing the BO. Fixes: d25e35bc26c3 ("drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain") Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Clean up suspend_all and resume_all mesAmber Lin1-43/+10
Compute user bad/hung queue recovery was handled by KFD using suspend_all_queues_mes, remove_queue(or reset_queue), and resume_all_queues_mes. Since now those steps are centralized to amdgpu_gfx_reset_mes_compute function to sync up with KCQ and KGD user queues, clean up redundant code and rename the function to match its functionality. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: Disable ras_check_bad_page_status on VFsVictor Skvortsov1-1/+4
Host driver determines the bad_page_status, not VF. VFs do not have access to the EEPROM, and eeprom_init is skipped. However, check_bad_page_status is called outside of the eeprom_init sequence without any is_vf checks. Add a return false in __is_ras_eeprom_supported for VFs, and use that guard in amdgpu_ras_check_bad_page_status to prevent incorrect access to un-initialized eeprom_control object. Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/pm: Validate OD DPM triples before mutating tablesAsad Kamal2-28/+43
vega10_odn_edit_dpm_table() and smu7_odn_edit_dpm_table() could mutate the live ODN table for valid triples, then return 0 after detecting a truncated buffer or out-of-range index. Validate all (index, clock, voltage) triples first and return -EINVAL on any failure; only then apply updates. v2: Use distinct message for different error case, removed unused input_level from validation loop (Lijo) v3: Reject negative level indices, input[] is long but was compared only against unsigned table bounds, so negative values could pass and truncate when assigned to uint32_t input_level. Set DPMTABLE_OD_UPDATE_SCLK/MCLK only after validation passes, so a failed sysfs write does not leave need_update_dpm_table set for a later commit. Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/pm: Validate custom profile parametersLijo Lazar7-18/+34
Add helpers to validate custom profile params against negative/out-of-range values. Use the helpers to validate user passed params. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Assisted-by: Claude Sonnet (Cursor AI) Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: Gate debugfs MMIO access on kernel lockdownAsad Kamal1-0/+7
amdgpu_regs, amdgpu_regs2, and related debugfs nodes allow arbitrary MMIO read/write via RREG32/WREG32 without checking security_locked_down(). On kernel_lockdown=integrity systems this bypasses the same restrictions as /dev/mem and PCI config space sysfs. Check LOCKDOWN_PCI_ACCESS (matching pci-sysfs) at the entry of every debugfs handler that performs direct register access. v2: Use consistent check as per previous check to use LOCKDOWN_DEBUGFS(Lijo) v3: Do not create any entry from amdgpu_debugfs_regs_init() if LOCKDOWN_PCI_ACCESS is active and log once. (Lijo) Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: add ioctl to handle RAS poison errorYifan Zhang7-1/+152
Add a new DRM_IOCTL_AMDGPU_PROC_OPTIONS ioctl with the AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY option, allowing userspace (ROCr) to control per-process SIGBUS delivery. Userspace for this can be found at: https://github.com/ROCm/rocm-systems/pull/6190 Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Pass known bad queue info to resetAmber Lin1-15/+15
suspend_all, resume_all, and remove bad queue has been integrated to a centralized function, amdgpu_gfx_reset_mes_compute. Remove remove_queue and resume_all in KFD and pass the known bad queue information required for remove_queue to amdgpu_gfx_reset_mes_compute. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: Expand MES queue/pipe reset supportAmber Lin1-1/+5
MES in newer versions on gfx11 and gfx12 can support queue/pipe reset via MES. v2: update the fw version check (Jesse) Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: Remove faulty queue before resumeAmber Lin6-6/+23
When driver already knows a bad queue but MES suspend_all is successful and MES hung queue detection doesn't detect it, remove this queue refore resume_all. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/mes12: enable compute MMIO pipe resetAlex Deucher1-3/+0
Enable MMIO pipe reset for compute pipes. Reviewed-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.54.0.dirty) at 2026-10-01 01:53:01 +0000