summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2026-07-27arm64: dts: ls1088a: describe the Lynx 10G SerDes blocksIoana Ciornei1-0/+58
Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS1088A SoC. The nodes are left disabled at the SoC level; board DTs will enable them once there are consumers. Note that the SerDes block #2 is non-networking, meaning that it will not get probed by the Lynx10G SerDes PHY driver and it's only added for a complete hardware description. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: ls208xa: describe the Lynx 10G SerDes blocksVladimir Oltean1-0/+98
Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS208xA SoC. The nodes are left disabled at the SoC level; board DTs will enable them once there are consumers. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: ls1046a: describe the Lynx 10G SerDes blocksVladimir Oltean1-0/+60
Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS1046A SoC. The nodes are left disabled at the SoC level; board DTs will be expected to enable them once the consumer Ethernet nodes appear. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: ls1028a: describe the Lynx 10G SerDesVladimir Oltean1-0/+29
Describe the Lynx 10G SerDes block and its 4 SerDes lanes found on the LS1028A SoC. The node is left disabled at the SoC level; board DTs will be expected to enable it once the consumer Ethernet nodes use it. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: lx2162a: transition to device-specific SerDes compatible stringsIoana Ciornei1-2/+67
Align to the modern fsl,lynx-28g.yaml binding for the LX2162A SoC, where the SoC and SerDes instance is present in the compatible string, to allow reliable per-lane capability detection and per-lane customization of electrical properties. Since one of the major differences between LX2162A and LX2160A is the SerDes, add the necessary nodes to its own fsl-lx2162a-serdes.dtsi file. Also mark the serdes_1 node as disabled by default since any dts using it enables it explicitly now. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: lx2160a: transition to device-specific SerDes compatible stringsIoana Ciornei1-2/+148
Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes instance is present in the compatible string, to allow reliable per-lane capability detection and per-lane customization of electrical properties. The modern bindings are backward-incompatible with old kernels, due to the consumer phandles being either in one form or in another, as explained here: https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/ Also mark the serdes_1 node as disabled by default since any dts using it enables it explicitly now. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: lx2160a: split the dtsi to avoid delete-propertyIoana Ciornei12-127/+234
Reorganize the LX216XA related dts/dtsi files with the intent to avoid any delete-property usage. Taken into consideration the differences between the LX2160A Rev1, LX2160A Rev2 and LX2162A SoCs, the following structure is created: fsl-lx216x.dtsi ---> fsl-lx2160a-rev1.dtsi (PCIe gen4, 3 SerDes blocks) (no PCIe, no SerDes) ---> fsl-lx2160a-rev2.dtsi (PCIe gen3, 3 SerDes blocks) ---> fsl-lx2162a.dtsi (PCIe gen3, 2 SerDes blocks) Each PCIe integration or SerDes block instantiation has its own dtsi file which gets to be included only by the necessary SoC level dtsi file. The dtsi file describing the PCIe controllers found on LX2160A Rev2 is also changed so that it does not work on a already defined node but rather it describes it entirely. In order to decouple the LX2162A from LX2160A, a new dtsi fsl-lx2162a-serdes.dtsi file is added which, for the moment, only duplicates the SerDes related nodes found already for LX2160A. Any dts which previously included fsl-lx2160a.dtsi now includes the -rev1 version and any dts which is clearly intended for LX2162A based board now includes the fsl-lx2162a.dtsi. No changes for the final dtbs. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: lx2160a: extract the PCIe from LX2160A Rev2 into a separate fileIoana Ciornei2-184/+188
The LX2160A Rev2 SoC changed the PCIe controllers used. This difference is reflected in the fsl-lx2160a-rev2.dtsi file which modifies the relevant dt nodes so that they match the actual HW. Extract these modifications into a separate dtsi file as a first step into a complete overhaul of the LX216xA related dts files with the intent to not use delete-node or delete-property. No final dtb changes are expected with this patch. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: lx2160a: extract the SerDes nodes into a separate dtsiIoana Ciornei2-13/+22
In terms of its SerDes blocks, the LX2162A is not properly described since it just inherits the LX2160A SerDes nodes, which is not correct. In order to fix this but also avoid the usage of delete-node, extract the SerDes nodes currently found in fsl-lx2160a.dtsi into a separate dtsi. No any actual changes in the final dtb files, only a dt node move. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: lx2160a: extract the PCIe nodes into a separate dtsiIoana Ciornei2-168/+178
One of the major differences between LX2160A Rev1 and Rev2 is the PCIe controller used. With the final goal of removing any usage of delete-node or delete-property from the current LX2160A related dts files, move the PCIe nodes found on the LX2160A Rev1 into a separate dtsi file. This will make it easier to include the appropriate dtsi file describing the PCIe controller depending on the SoC revision in a follow-up patch. No actual change in the DT nodes found in the final DTBs is intended. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arm64: dts: lx2160a: explicitly enable serdes_1 nodeIoana Ciornei4-0/+16
Explicitly enable the serdes_1 node in all board DT files. This is needed in order to be able to change the default status of the node to "disabled" from the SoC DT file. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-27arch: hookup fchroot() system callChristian Brauner16-0/+16
Wire up the fchroot() system call as number 472 on (nearly) all architectures and sync the mirrored copies of the syscall tables and the asm-generic unistd.h under tools/. Link: https://patch.msgid.link/20260724-work-failfs-v2-5-485dabbae185@kernel.org Signed-off-by: Christian Brauner (Amutable) <brauner@kernel.org>
2026-07-27Merge tag 'renesas-dts-for-v7.3-tag1' of ↵Arnd Bergmann29-112/+1461
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v7.3 - Add sound support for the RZ/G3E SoC and the RZ/G3E SMARC EVK board, - Add more serial and SPI support for the RZ/G3L SoC and the RZ/G3L SMARC EVK board, - Add SMP support (32x Cortex-A720AE) for the R-Car X5H SoC, - Add hwspinlock and mailbox (MFIS) support for the R-Car V4H SoC, - Add GPU support for R-Car M3-N-based Salvator-X(S) and ULCB development boards, - Add SPI and FRAM support for the RZ/N1D SoC and the RZN1D Expansion Board, - Add PCIe support for the RZ/V2H SoC and the RZ/V2H EVK development board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v7.3-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits) arm64: dts: renesas: r9a09g047: Fix PCIe dma-ranges memory space code arm64: dts: renesas: r9a09g056: Fix PCIe dma-ranges memory space code arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable PCIe arm64: dts: renesas: r9a09g057: Add PCIe nodes ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM ARM: dts: renesas: r9a06g032: Describe SPI controllers arm64: dts: renesas: rzt2h-n2h-evk-common: Add memory nodes arm64: dts: renesas: Add soc: labels to soc nodes arm64: dts: renesas: r9a09g047e57-smarc: Add DA7212 audio codec support arm64: dts: renesas: rzg3e-smarc-som: Add audio pinmux definitions arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator arm64: dts: renesas: r9a09g047: Add RZ/G3E Sound support arm64: dts: renesas: r8a77965-ulcb: Enable GPU support arm64: dts: renesas: r8a77965-salvator-xs: Enable GPU support arm64: dts: renesas: r8a77965-salvator-x: Enable GPU support ARM: dts: renesas: r8a7740: Add FSI clocks arm64: dts: renesas: r9a09g047: Add max-frequency to SDHI nodes arm64: dts: renesas: r9a09g047e57-smarc: Drop SW_SER0_PMOD condition for rsci4 arm64: dts: renesas: r8a779g0: Add MFIS node arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-27Merge tag 'config-gpio-legacy-for-7.3' of ↵Bartosz Golaszewski27-22/+34
https://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground into gpio/for-next gpio: legacy interface cleanups for 7.3 These are the remaining patches for legacy gpio interface cleanup, ensuring that files referencing them are sure to have CONFIG_GPIOLIB_LEGACY set, and use linux/gpio/legacy.h instead of the old linux/gpio.h header. There are a few more patches already merged in other branches for 7.3, including soc, led, net and media. Once everything is in, we can apply the final patches to turn off CONFIG_GPIOLIB_LEGACY by default and remove the obsolete header file. This branch is based on the immutable ib-mfd-legacy-gpio-7.3 branch from mfd.git to avoid a conflict in the rohm drivers.
2026-07-27Merge tag 'lpc32xx-arm-for-7.3' of ↵Arnd Bergmann4-68/+6
https://github.com/vzapolskiy/linux-lpc32xx into soc/arm ARM: nxp: lpc32xx: ARM changes for v7.3 NXP LPC32xx ARM changes for v7.3 contain: - Karl Mehltretter fixes a multiplatform kernel runtime execution by limiting LPC32xx SoC specific init functions to be run on this platform only, - a stale method of populating DMA, SLC and MLC NAND controllers is removed from platform code, this change was announced to happen by the end of this year, all touched by the change controllers are properly described in the platform device tree for years, and very old board dtbs are recommended to be updated. * tag 'lpc32xx-arm-for-7.3' of https://github.com/vzapolskiy/linux-lpc32xx: ARM: lpc32xx: remove a few manually populated OF devices ARM: lpc32xx: only run SoC init on LPC32xx hardware Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-27KVM: s390: Fall back to short-term pinning in MAP ioctlJaehoon Kim2-14/+47
FOLL_LONGTERM pinning fails for some memory types, such as file-backed guest memory. As a result, kvm_s390_adapter_map() returns -EINVAL and irqfd adapter registration fails even though interrupt delivery could still work via the existing non-atomic path. When FOLL_LONGTERM pinning fails, verify that the page is accessible using a short-term pin instead. If the short-term pin succeeds, unpin the page and add a map entry with pinned=false to preserve MAP/UNMAP symmetry. The non-atomic irqfd path already performs short-term pinning for interrupt delivery, so this restores the previous behavior for memory that cannot be pinned long-term. get_map_info() is updated to return NULL for unpinned entries so that the atomic irqfd fast path falls back to the non-atomic path. kvm_s390_adapter_unmap() and kvm_s390_unmap_all_adapters() skip dirty marking and unpin for unpinned entries. Update Documentation/virt/kvm/devices/s390_flic.rst to reflect the new MAP/UNMAP behavior. Fixes: c9a568838086 ("KVM: s390: Add map/unmap ioctl and clean mappings post-guest") Signed-off-by: Jaehoon Kim <jhkim@linux.ibm.com> Reviewed-by: Douglas Freimuth <freimuth@linux.ibm.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@linux.ibm.com>
2026-07-27arm64: dts: microchip: lan969x: add QSPI nodesRobert Marko1-0/+33
Add the required DT nodes for both QSPI controllers. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20260709112006.390742-6-robert.marko@sartura.hr Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-07-26Merge tag 'm68knommu-fixes-on-top-off-7.2-rc4' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu Pull m68knommu fix from Greg Ungerer: - fix broken local SoC IO accesses for ColdFire * tag 'm68knommu-fixes-on-top-off-7.2-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68k: coldfire: fix breakage of missed IO access update
2026-07-26Merge tag 'x86-urgent-2026-07-26' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fix from Ingo Molnar: - Disable jump/lookup tables in the x86 boot decompressor code a bit more widely, because newer versions of LLVM started optimizing it a bit better and introduced run-time relocations in PIE code (Nathan Chancellor) * tag 'x86-urgent-2026-07-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/boot/compressed: Disable jump tables
2026-07-26arm64: futex: Consolidate 'old == new' check in __lsui_cmpxchg32()Will Deacon1-39/+22
The LSUI futex implementation relies on a cmpxchg() loop to implement FUTEX_OP_XOR, as the architecture doesn't provide unprivileged *EOR atomics. Since the unprivileged 'CAST' instructions used to implement the cmpxchg() can only operate on 64-bit memory locations, the __lsui_cmpxchg32() helper function performs a song and dance to marshall the 32-bit futex value into the correct part of a 64-bit register and fill the remaining bytes with the neighbouring data. A consequence of this structure is that the 'CAST' failure/success condition ends up being split into two separate 32-bit checks across __lsui_cmpxchg32() and its caller. This is a little fiddly to read and introduces some additional local variables which can be avoided if the check is done in one place. Tweak __lsui_cmpxchg32() so that it performs the full 64-bit check on the value returned from the 'CAST' instruction and returns success to its caller only in the case that the cmpxchg() operation has succeeded. With that in place, simplify the outer loop in __lsui_futex_atomic_eor() to pass 'oldval' by reference and return unless the cmpxchg() operation returns -EAGAIN. __lsui_futex_cmpxchg() then swallows the -EAGAIN if the futex word has changed. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Yeoreum Yun <yeoreum.yun@arm.com> Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-26arm64: RSI: fix field-spanning write warning in attestation token initKohei Enju1-8/+19
The challenge is passed in registers a1 through a8. However, copying to &regs.a1 makes FORTIFY treat the destination as the single a1 field, resulting in a field-spanning write warning. [1] Overlay the SMCCC register structure with an RSI-specific argument layout and copy the challenge into an explicit 64-byte array. This keeps the existing a1-a8 argument encoding while giving the copy a correctly sized destination object. [1] memcpy: detected field-spanning write (size 64) of single field "&regs.a1" at ./arch/arm64/include/asm/rsi_cmds.h:119 (size 8) WARNING: ./arch/arm64/include/asm/rsi_cmds.h:119 at rsi_attestation_token_init+0xdc/0xf8 [arm_cca_guest], CPU#0: cat/3314 Fixes: b880a80011f5 ("arm64: rsi: Add RSI definitions") Signed-off-by: Kohei Enju <enju.kohei@fujitsu.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-26x86/bugs: Make Safe-RET robust against interrupt injectionBorislav Petkov (AMD)4-1/+123
An attacker injecting interrupts while the Safe-RET mitigation executes on machines affected by SRSO can neutralize the safe return sequence, potentially leading to data leakage through speculative execution. Fixup register state as if the Safe-RET sequence executed successfully by "emulating" it, in a manner of speaking, and avoid executing a RET instruction after returning from the interrupt. Co-developed-by: David Kaplan <David.Kaplan@amd.com> Signed-off-by: David Kaplan <David.Kaplan@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
2026-07-26riscv: dts: spacemit: enable PCIe on OrangePi R2SChukun Pan1-0/+38
Enable the two RTL8125 network controllers and corresponding PHYs connected via the PCIe controllers on the OrangePi R2S. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260602100000.2402784-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-26riscv: dts: spacemit: k3-com260-ifx: add eeprom on i2c1Jennifer Berringer2-0/+27
Enable i2c1 for k3-com260-ifx and use it for a 24c02 eeprom. This eeprom, unlike the one connected to i2c2, is part of the carrier board. Some boards do not have any data programmed on this eeprom from factory. Signed-off-by: Jennifer Berringer <jberring@redhat.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260722202848.1817988-3-jberring@redhat.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-26riscv: dts: spacemit: k3-com260: add eeprom on i2c2Jennifer Berringer1-0/+32
Enable i2c2 on the K3 CoM260 compute module and use it for a 24c02 eeprom. This eeprom stores the product name, a MAC address, and a serial number. Signed-off-by: Jennifer Berringer <jberring@redhat.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260722202848.1817988-2-jberring@redhat.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-26riscv: dts: spacemit: add SPI controllers for K3Zhengyu He1-1/+48
Add the SPI controller nodes for K3. Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-3-969a1b0f783f@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-26riscv: dts: spacemit: add K3 PDMA request numbersliyeshan1-0/+83
Add a local DTS header that gives symbolic names to the SpacemiT K3 PDMA request lines of the non-secure peripherals. Device trees can use these K3_PDMA_* macros instead of hard-coded request numbers when wiring a peripheral "dmas" property. Signed-off-by: liyeshan <yeshan.li@spacemit.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-1-969a1b0f783f@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-26riscv: dts: spacemit: Fix phy id check for the phy on com260 boardInochi Amaoto1-1/+1
Current phy framework can not re-initialize the phy correctly, as it will assert the phy reset GPIO so the phy id can not be read. Setting the phy id of board com260 manually so the phy id dectection can be skipped. Fixes: cfe5c91cb73c ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260725233351.55004-3-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-26riscv: dts: spacemit: Fix phy id check for the phy on pico-itx boardInochi Amaoto1-1/+1
Current phy framework can not re-initialize the phy correctly, as it will assert the phy reset GPIO so the phy id can not be read. Setting the phy id of board pico-itx manually so the phy id detection can be skipped. Fixes: 74657a376960 ("riscv: dts: spacemit: Add ethernet device for K3") Reported-by: E Shattow <e@freeshell.de> Reported-by: Inochi Amaoto <inochiama@gmail.com> Closes: https://lore.kernel.org/netdev/20260712045233.800748-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Tested-by: E Shattow <e@freeshell.de> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260725233351.55004-2-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-25arm64: dts: amd: seattle: Remove useless xgbe DTSI includeKrzysztof Kozlowski2-85/+77
The "amd-seattle-xgbe-b.dtsi" file is included exactly once, so paste the contents directly in proper DTSI. No functional impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260706093523.274093-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-07-25arm64: dts: amd: seattle: Remove useless clocks DTSI includeKrzysztof Kozlowski2-44/+35
The "amd-seattle-clks.dtsi" file is included exactly once, so paste the contents directly in proper DTSI. No functional impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260706093523.274093-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-07-25ARM: dts: nvidia: tegra114-asus-tf701t: Correct trailing whitespaceKrzysztof Kozlowski1-1/+1
Drop trailing whitespace. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260706101757.340149-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-07-25ARM: dts: vt8500: Correct indentationKrzysztof Kozlowski4-85/+85
Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260706101805.341103-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-07-25ARM: dts: microchip: at91: Correct indentationKrzysztof Kozlowski2-8/+8
Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260706101843.341339-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-07-25ARM: dts: arm: Correct indentationKrzysztof Kozlowski5-10/+10
Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://patch.msgid.link/20260706101942.341681-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-07-25ARM: dts: sigmastar: Correct indentationKrzysztof Kozlowski1-10/+10
Correct indentation to one tab. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Daniel Palmer <daniel@thingy.jp> Link: https://patch.msgid.link/20260706180404.648545-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-07-25Merge tag 'loongarch-fixes-7.2-1' of ↵Linus Torvalds8-21/+50
git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson Pull LoongArch fixes from Huacai Chen: - fix build warnings and errors - move jump_label_init() before parse_early_param() - retrieve CPU package ID from PPTT when available - fix some bugs kgdb, BPF JIT and laptop platform driver bugs * tag 'loongarch-fixes-7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: platform/loongarch: laptop: Explicitly reset bl_powered state when suspend platform/loongarch: laptop: Stop setting acpi_device_class() LoongArch: BPF: Fix memory leak in bpf_jit_free() LoongArch: BPF: Zero-extend signed ALU32 div/mod results LoongArch: Fix oops during single-step debugging LoongArch: Fix address space mismatch in kexec command line lookup LoongArch: Retrieve CPU package ID from PPTT when available LoongArch: Move jump_label_init() before parse_early_param() LoongArch: Fix build errors due to wrong instructions for 32BIT LoongArch: Increase TASK_STRUCT_OFFSET up to 2040 for 32BIT
2026-07-24Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf 7.2-rc5Eduard Zingerman41-114/+275
Cross-merge BPF and other fixes after downstream PR. Conflicts: net/core/filter.c Changes [2] in bpf-next conflict with a recent fix [1] from the 'net' tree. Resolved by using [1] as a base and applying same flags handling logic as in [2] in the bpf_redirect_peer() helper. [1] https://lore.kernel.org/all/20260706185609.330006-2-daniel@iogearbox.net/ [2] https://lore.kernel.org/all/20260618182035.43811-2-jordan@jrife.io/ Signed-off-by: Eduard Zingerman <eddyz87@gmail.com>
2026-07-25riscv: dts: spacemit: Add enough deassert time for the PHY on com260 boardInochi Amaoto1-1/+1
RTL8211F require at least 50ms deassert to guarantee the register access, 10ms is only enough for the PHY reset. Fixes: cfe5c91cb73c ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://patch.msgid.link/20260710063314.1030249-2-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-25riscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITXInochi Amaoto1-1/+1
RTL8211F require at least 50ms deassert to guarantee the register access, 10ms is only enough for the PHY reset. Fixes: 74657a376960 ("riscv: dts: spacemit: Add ethernet device for K3") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Tested-by: E Shattow <e@freeshell.de> Link: https://patch.msgid.link/20260710063314.1030249-1-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-24s390/bpf: Support load-acquire and store-release instructionsMaxim Khmelevskii1-8/+23
Support load-acquire (BPF_LOAD_ACQ) and store-release (BPF_STORE_REL) instructions. Since s390 has strong memory model, implement them as regular BPF_LDX/BPF_STX instructions. Tested with: ./test_progs -t verifier_load_acquire,verifier_store_release,atomics Signed-off-by: Maxim Khmelevskii <max@linux.ibm.com> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Link: https://lore.kernel.org/bpf/20260723140648.583055-7-max@linux.ibm.com Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
2026-07-24s390/bpf: Add emit_ldx and emit_stx functionsMaxim Khmelevskii1-85/+82
Add new functions for load and store to reuse them in the load-acquire and store-release logic. Signed-off-by: Maxim Khmelevskii <max@linux.ibm.com> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Link: https://lore.kernel.org/bpf/20260723140648.583055-6-max@linux.ibm.com Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
2026-07-24ARM: dts: ls1021a-iot: rename display@0 to display0Frank Li1-2/+2
Rename node name display@0 to display0 since no reg under it. Rename mode0 to timing0. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-iot.dtb: dcu@2ce0000 (fsl,ls1021a-dcu): 'display', 'display@0' do not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/display/fsl,ls1021a-dcu.yaml arch/arm/boot/dts/nxp/ls/ls1021a-iot.dtb: display-timings: 'mode0' does not match any of the regexes: '^pinctrl-[0-9]+$', '^timing' from schema $id: http://devicetree.org/schemas/display/panel/display-timings.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-24ARM: lpc32xx: remove a few manually populated OF devicesVladimir Zapolskiy1-60/+0
For a good while the common for all NXP LPC32xx platforms lpc32xx.dtsi file contains proper descriptions of DMA, SLC and MLC NAND controllers, this allows to remove populated device tree nodes from platform code. At the end of the last year it was announced that this change to happen, unlikely there are still users with such old dtbs to be affected by this change, but if there are such users, they should update board dtb file, if DMA or NAND controller decriptions are not found in them. Signed-off-by: Vladimir Zapolskiy <vz@kernel.org> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-07-24ARM: lpc32xx: only run SoC init on LPC32xx hardwareKarl Mehltretter4-8/+6
lpc32xx_check_uid() and lpc32xx_pm_init() are arch_initcalls that poke LPC32xx-only registers. Since the multiplatform conversion they also run on other ARCH_MULTI_V5 boards where access faults e.g. on versatile: Unable to handle kernel paging request at virtual address f4004130 PC is at lpc32xx_check_uid+0x2c/0x9c Drop the arch_initcall() registrations and call both functions directly from lpc3250_machine_init(), the machine's .init_machine hook. The calls are placed in link order (common.c, pm.c, phy3250.c) to keep their previous relative ordering. Fixes: 75bf1bd7d2f9 ("ARM: lpc32xx: allow multiplatform build") Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Karl Mehltretter <kmehltretter@gmail.com> Reviewed-by: Vladimir Zapolskiy <vz@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-07-24bpf, riscv: Add support for timed may_gotoFeng Jiang3-2/+59
Implement arch_bpf_timed_may_goto() for the RV64 JIT. The argument and return value are carried in BPF_REG_AX, and BPF R0-R5 are preserved across the call to the generic bpf_check_timed_may_goto(). Enable bpf_jit_supports_timed_may_goto() so the verifier uses the timed expansion path. Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn> Reviewed-by: Pu Lehui <pulehui@huawei.com> Reviewed-by: Björn Töpel <bjorn@kernel.org> Acked-by: Björn Töpel <bjorn@kernel.org> Link: https://lore.kernel.org/bpf/20260723-riscv-bpf-timed-may-goto-v5-1-86acb54e5642@kylinos.cn Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
2026-07-24KVM: SVM: Always intercept ICEBP to workaround AMD ICEBP+TASK_SWITCH flawsDavid Woodhouse1-0/+18
Unconditionally intercept and emulate ICEBP, i.e. INT1 #DBs, on SVM to workaround a bug/misfeature in current AMD CPUs. AMD CPUs don't provide information to allow software to distinguish instruction-induced #DBs (i.e. ICEBP) from exception-induced #DBs (all others), and also don't report an instruction length for an ICEBP-induced TASK_SWITCH. On an intercepted TASK_SWITCH (which always has fault semantics), KVM (any hypervisor, really) looks at the vectoring event type to decide whether it was logically caused by a trap, and therefore whether to advance guest RIP before entering the new task. If the guest IDT is configured to deliver #DBs via a task gate, then the guest will see broken behavior for ICEBP #DB because KVM doesn't have enough information to detect and skip the ICEBP. The typical workaround is to intercept ICEBP unconditionally and handle the FAULT=>TRAP conversion in the hypervisor, at which point the #DB-induced TASK_SWITCH occurs with RIP on the correct instruction boundary regardless of whether it was instruction-induced or exception-induced. As a bonus, intercepting ICEBP more or less aligns SVM with VMX (KVM always intercepts #DBs on VMX, and ICEBP #DB VM-Exits on Intel have fault-like behavior). Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Link: https://patch.msgid.link/e03f092dfbb7d391a6bf2797ba01e122ba080bcd.camel@infradead.org [sean: drop selftest, reword changelog to provide more details] Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-24arm64: dts: rockchip: Fix rk3566-bigtreetech-cb2 touchscreen propertyFabio Estevam1-1/+1
The TSC2007 driver uses the ti,max-rt property to specify the maximum touch resistance, but the rk3566-bigtreetech-cb2 device tree uses the undocumented ti,rt-thr property instead. As a result, the configured value is ignored and the driver falls back to its default maximum resistance value of 4095. Replace ti,rt-thr with ti,max-rt to preserve the intended resistance threshold of 3000. Fixes: bfbc663d2733 ("arm64: dts: rockchip: Add BigTreeTech CB2 and Pi2") Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://patch.msgid.link/20260721135450.45286-1-festevam@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-07-24arm64: dts: rockchip: fix label of sys_led for nanopi-r4sVic B1-3/+7
This commit corrects the system LED configuration for the NanoPi R4S by replacing the deprecated label property with color and function. This changes the resulting label of mislabeled sys_led from red:power to green:status, while the labels of the other two leds stay intact (green:lan for lan_led and green:wan for wan_led). Signed-off-by: Vic B <linux@vicb.net> Link: https://patch.msgid.link/al0cKhqvPbBO_5q8@vicb.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-07-24arm64: dts: rockchip: Fix the rk3566-radxa-cm3 Wifi compatibleFabio Estevam1-1/+1
According to brcm,bcm4329-fmac.yaml, "brcm,bcm43455-fmac" needs the "brcm,bcm4329-fmac" fallback. Change it accordingly to fix the following dt-schema warning: ['brcm,bcm43455-fmac'] is too short Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://patch.msgid.link/20260721133421.44258-1-festevam@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit (git 2.54.0.dirty) at 2026-09-23 15:02:04 +0000