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2026-08-06s390/dasd: Add __context_unsafe() attribute to various functionsHeiko Carstens1-0/+7
Disable context analysis for various functions to get rid of context analysis compile time warnings using clang caused by conditional locking like e.g.: drivers/s390/block/dasd_eckd.c:1462:3: warning: releasing mutex 'dasd_pe_handler_mutex' that was not held [-Wthread-safety-analysis] 1462 | mutex_unlock(&dasd_pe_handler_mutex); | ^ Use __context_unsafe() to provide a short comment why context analysis is disabled for each function. It doesn't look like those functions can be easily reworked to get rid of conditional locking. Therefore disable context analysis for (only) those functions. Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Acked-by: Stefan Haberland <sth@linux.ibm.com> Link: https://patch.msgid.link/20260806130050.2057443-2-hca@linux.ibm.com Signed-off-by: Jens Axboe <axboe@kernel.dk>
2026-08-06leds: pca963x: Add multicolor LED class supportLoic Poulain2-42/+148
Allow grouping of individual PCA963x PWM channels into a single multicolor LED device by adding support for the LED multicolor class. A child node with sub-children is treated as a multicolor group, others are treated as single leds, keeping full backwards compatibility. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Link: https://patch.msgid.link/20260727-monza-leds-v8-3-6e7e93d44dba@oss.qualcomm.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06dt-bindings: leds: nxp,pca963x: Add multicolor LED supportLoic Poulain1-2/+94
Add support for grouping individual PCA963x channels into a multicolor LED by introducing a multi-led@N node pattern. This follows the convention established by other multicolor LED drivers such as kinetic,ktd202x. This is necessary to support and model hardware setups where multiple PWM channels drive a single physical RGB LED. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Link: https://patch.msgid.link/20260727-monza-leds-v8-2-6e7e93d44dba@oss.qualcomm.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06dt-bindings: leds: nxp,pca963x: Fix reg maximum for pca9635Loic Poulain1-3/+9
The pca9635 supports 16 LED channels, unlike the pca9634 which only supports 8. The allOf conditional grouped both chips under a single else branch capping reg at a maximum of 7. Give pca9634 its own if/then block and set maximum: 15 unconditionally in the top-level led@ node, making it the default for pca9635 and any future compatible. Also tighten the node name regex from [0-9a-f]+ to [0-9a-f] to match the single-digit hardware limit. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Link: https://patch.msgid.link/20260727-monza-leds-v8-1-6e7e93d44dba@oss.qualcomm.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06rust: io: gate ioremap doctests on CONFIG_HAS_IOMEMDanilo Krummrich2-0/+2
The doc examples in io.rs and devres.rs directly call bindings::ioremap() and bindings::iounmap(), which do not exist when CONFIG_HAS_IOMEM is not set. This causes build failures with CONFIG_RUST_KERNEL_DOCTESTS=y on such configurations (e.g. s390 allnoconfig). Gate the affected doctests with `#![cfg(CONFIG_HAS_IOMEM)]` so they are skipped when IOMEM is unavailable. Fixes: 3f70ebe63858 ("s390: Enable Rust support") Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260805212920.1996937-2-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-08-06rust: io: gate ioremap/iounmap on CONFIG_HAS_IOMEMDanilo Krummrich3-4/+8
s390 does not provide ioremap()/iounmap() when CONFIG_HAS_IOMEM is not set (which requires CONFIG_PCI on that architecture). This causes a build failure with Rust enabled on e.g. s390 allnoconfig: In file included from rust/helpers/helpers.c:68: rust/helpers/io.c:8:9: error: call to undeclared function 'ioremap'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 8 | return ioremap(offset, size); | ^ rust/helpers/io.c:19:2: error: call to undeclared function 'iounmap'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 19 | iounmap(addr); Guard the C helpers behind #ifdef CONFIG_HAS_IOMEM and cfg-gate the Rust io::mem module, such that IoMem, ExclusiveIoMem and IoRequest are not available without CONFIG_HAS_IOMEM. Note that the C API is inconsistent about this. For instance, devm_ioremap() has no stub and produces a link failure without CONFIG_HAS_IOMEM, whereas devm_platform_ioremap_resource() provides an inline stub returning -EINVAL. The approach taken here (compile-time gating) matches the former, which is slightly more appropriate since any driver performing MMIO currently requires CONFIG_HAS_IOMEM. Ideally, s390 should provide ioremap()/iounmap() stubs unconditionally (as UML already does), removing the need for any config gating as discussed in [1]; a follow-up patch for s390 is expected. Cc: Arnd Bergmann <arnd@arndb.de> Reported-by: Miguel Ojeda <ojeda@kernel.org> Closes: https://lore.kernel.org/all/20260803180931.97202-1-ojeda@kernel.org [1] Fixes: 3f70ebe63858 ("s390: Enable Rust support") Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260805212920.1996937-1-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-08-06drm/amd/display: Add KUnit tests for crtc set_static_screen_optimzeBhawanpreet Lakha1-0/+55
Add dm_test_crtc_set_static_screen_optimze_sr_entry_psr and dm_test_crtc_set_static_screen_optimze_psr_su_skips to cover the allow_sr_entry == true path of amdgpu_dm_crtc_set_static_screen_optimze(): the replay/PSR event updates when psr_version < DC_PSR_VERSION_SU_1, and skipping the PSR event update when psr_version is DC_PSR_VERSION_SU_1. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add KUnit tests for crtc set_vupdate_irqBhawanpreet Lakha1-0/+99
Add dm_test_crtc_set_vupdate_irq_dc_busy and dm_test_crtc_set_vupdate_irq_enable to cover the previously untested paths in amdgpu_dm_crtc_set_vupdate_irq() where an OTG instance is assigned: dc_interrupt_set() failing (returns -EBUSY) and succeeding via a mock IRQ service (returns 0 for enable and disable). Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add KUnit test for crtc vblank event completionBhawanpreet Lakha1-0/+45
Add dm_test_crtc_handle_vblank_completes_cursor_only to cover the previously untested branch in amdgpu_dm_crtc_handle_vblank() where a pending event with pflip_status != AMDGPU_FLIP_SUBMITTED (a cursor-only commit) is signalled: the vblank event is sent, the vblank reference is dropped, and acrtc->event is cleared. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add active plane count tests for crtcBhawanpreet Lakha3-1/+118
Expose amdgpu_dm_crtc_count_crtc_active_planes() for KUnit and add tests covering the empty plane list and the mixed case exercising the mask filter, cursor skip, missing plane state, and framebuffer presence branches. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add idle worker tests for crtcBhawanpreet Lakha5-1/+216
Expose amdgpu_dm_idle_worker() for KUnit and add tests covering the disabled exit, both loop break paths, and the enable-body path. Add dm_kunit_alloc_dc_state() and dm_kunit_alloc_clk_mgr() helpers to support the new tests. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add vblank handling tests for crtcBhawanpreet Lakha3-1/+218
Add KUnit coverage for the CRTC vblank paths: - amdgpu_dm_crtc_handle_vblank: no-event completion and the AMDGPU_FLIP_SUBMITTED guard that keeps a pending event pending. - amdgpu_dm_crtc_vblank_control_worker: enable increments, disable decrements, and disable clamps the active vblank IRQ count at zero. - amdgpu_dm_crtc_disable_vblank: disable path returns cleanly when the IRQ subsystem is not installed. Expose amdgpu_dm_crtc_vblank_control_worker for KUnit via STATIC_IFN_KUNIT/EXPORT_IF_KUNIT and declare it in the header. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add KUnit tests for more crtc functionsBhawanpreet Lakha3-4/+193
Expand KUnit coverage for amdgpu_dm_crtc.c with tests for functions that are easy to exercise in isolation: - amdgpu_dm_crtc_set_static_screen_optimze(): the !allow_sr_entry early return. - amdgpu_dm_crtc_enable_vblank(): rejection with -EINVAL when enabling vblank on an unconfigured CRTC. - amdgpu_dm_crtc_update_crtc_active_planes(): the no-stream branch that resets active_planes to zero. - amdgpu_dm_crtc_duplicate_state(): DM-specific fields are carried over. - amdgpu_dm_crtc_reset_state(): a fresh state is allocated and installed. - amdgpu_dm_crtc_destroy_state(): a stream-less state is freed cleanly. Expose amdgpu_dm_crtc_destroy_state(), amdgpu_dm_crtc_duplicate_state(), amdgpu_dm_crtc_reset_state() and amdgpu_dm_crtc_update_crtc_active_planes() to the tests via STATIC_IFN_KUNIT/EXPORT_IF_KUNIT. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Fix seamless mode switch not triggering for HDR to SDR ↵Karthi Kandasamy7-16/+60
transition [Why] The seamless mode switch was not getting triggered during HDR to SDR transitions, and no DPCD write was observed. Root cause analysis revealed that incorrect panel capabilities were being reported for PSR SU panels. Due to the wrong capabilities, the OS was not invoking the seamless mode switch API, resulting in no DPCD communication and also gated eDP teardown across the seamless mode switch hold. [How] Fixed by setting the correct power panel capabilities for PSR SU panels. This ensures the OS receives accurate panel capability information and triggers the seamless mode switch API as expected, restoring proper DPCD writes during HDR to SDR transitions. The DC commit sequence was tearing the eDP down anyway -- backlight off, ABM disable, DPMS off, PSR/Replay enable state cleared, PHY TX off, OTG/OPTC off; all these actions are blocked now with the skip_implict_edp_power_control Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Fix wb_info leak and NULL deref in writebackAlex Hung1-5/+11
[WHAT] dc_stream_add_writeback() copies wb_info by value, so free it on all paths via a single cleanup label. Also bail out early when no pipe_ctx matches the stream to avoid a NULL pointer dereference. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Gate HDMI FRL status polling on active FRL link rateFangzhi Zuo1-1/+1
[Why] hdmi_frl_status_polling_work() skipped any link whose connector_signal was not SIGNAL_TYPE_HDMI_FRL. connector_signal is not reliably set to SIGNAL_TYPE_HDMI_FRL while a link is actually running FRL, so links that were operating in FRL mode were skipped and their status flags never got polled, missing link-retrain events. [How] Use frl_link_settings.frl_link_rate to decide whether a link is running FRL. A non-zero rate means FRL is active, so only links with a zero rate are skipped. This ensures every link actually operating in FRL mode is polled for status changes. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Update VRR info packet to support 12-bit refresh ratesHarry VanZyllDeJong1-4/+4
[Why] VRR info packet previously only supported up to 10-bit refresh rate values limiting the range of FreeSync minimum and maximum refresh rates that could be encoded. [How] Expanded the bit masking in PB11/PB12 from 2 to 4 bits to capture bits 11:8 of the minimum and maximum FreeSync refresh rates, enabling the VRR info packet to encode 12-bit refresh rate values. Reviewed-by: Anthony Koo <anthony.koo@amd.com> Signed-off-by: Harry VanZyllDeJong <hvanzyll@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Ensure dtbclk is enabledCharlene Liu5-6/+46
[why] ensure dtbclk is enabled before hdmistreamclk_en pmfw could stop dtbclk on idle. driver needs to ensure dtbclk enabled is enabled before hdmistreamclk_en also disable debounce timer on dcn42. Reviewed-by: Chris Park <chris.park@amd.com> Reviewed-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Bounds-check connector->index in dm_dp_mst_get_modesHarry Wentland1-1/+2
dm_dp_mst_get_modes() uses drm_connector->index to index the per-connector HDCP arrays in struct hdcp_workqueue. Those arrays are sized to AMDGPU_DM_MAX_DISPLAY_COUNT, which matches the DRM connector index range (0..31). Add a defensive bounds check so that, should the DRM connector index range ever grow beyond the array size, the access is skipped instead of reading and writing out of bounds. Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Resize MST HDCP per-connector arrays to 32Harry Wentland2-10/+10
AMDGPU_DM_MAX_DISPLAY_INDEX is 31. It suggest a maximum number of 32 connectors. But the way it's used is like MAX_DISPLAY_COUNT. Hence we're off by one with DRM core, which supports a max of 32 connectors. Rename AMDGPU_DM_MAX_DISPLAY_INDEX to AMDGPU_DM_MAX_DISPLAY_COUNT to match its actual use, and increase the size to 32 to match the originally intended size. Fixes: 82986fd631fa ("drm/amd/display: save restore hdcp state when display is unplugged from mst hub") Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gfx6: Fixup emit_cntxcntl()Timur Kristóf1-7/+21
Set bits on dword 2 like GFX7-8 except load_global_uconfig which doesn't exist on GFX6. Emit VS_PARTIAL_FLUSH before VGT_FLUSH like GFX7-8. For reference see old PAL which explains the bit fields in this register and that load_global_uconfig doesn't exist on GFX6 and also see gfx_v7_ring_emit_cntxcntl() for the GFX7 code which this commit follows. Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si v8") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Remove duplicate in tests/MakefileRoman Li1-1/+0
The duplicate amdgpu_dm_plane_test.o entry causes linker errors during the arm-64 build. Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gmc12.1: fix MMHUB0 check in pasid tlb flushAlex Deucher1-1/+1
Check for mmhub0 rather than mmhub1. Looks like a copy paste typo. Fixes: d0c989a0aad3 ("drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12_1") Cc: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Enable DCN6 sources compilationAurabindo Pillai121-53/+3081
- Add hooks in various entry points to perform hw/sw init for DCN6 asic - Add dependent changes needed to enable DCN6 asic - Update the Makefiles so that DCN6 related newly added sources are compiled Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06leds: gpio: Clear error pointers for skipped LEDsSteve Dunnagan1-0/+1
gpio_led_get_gpiod() returns an error pointer when a platform-data LED's GPIO is unavailable. gpio_led_probe() skips registration in that case, but leaves the error pointer in led_dat->gpiod. The skipped entry remains included in priv->num_leds. During shutdown, gpio_led_shutdown() walks those entries and passes the error pointer to gpio_led_set(), producing: gpiod_set_value: invalid GPIO (errorpointer: -ENOENT) Clear led_dat->gpiod before skipping the LED so skipped entries do not retain error-valued descriptors. Fixes: 45d4c6de4e49 ("leds: gpio: Try to lookup gpiod from device") Suggested-by: Lee Jones <lee@kernel.org> Assisted-by: ChatGPT:GPT-5.5-Thinking Signed-off-by: Steve Dunnagan <sdunnaga@redhat.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260724180412.43150-1-sdunnaga@redhat.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06drm/amdgpu: Allocate coredump ring buffers per ringLijo Lazar2-26/+27
Allocate each ring buffer separately. A single allocation summing all ring sizes can exceed the page allocator's MAX_ORDER limit and fail; per-ring buffers stay small enough to satisfy. The existing allocation style doesn't capture any ring data if the huge allocation fails. Splitting into multiple allocations helps to capture as much data as possible for the core dump. A failed ring is left with a NULL buffer and skipped when formatting. Fixes: eea85914d15b ("drm/amdgpu: save ring content before resetting the device") Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Assisted-by: Claude Code Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: Use virtual alloc during coredumpLijo Lazar1-3/+7
The number of rings with outstanding fences can be large, requiring a bigger allocation. Such allocations don't need to be physically contiguous, so use kvzalloc/kvcalloc which fall back to vmalloc when contiguous memory isn't available. This also matches the existing kvfree used to free these allocations. Also guard the allocation with ring_count to avoid passing 0 size to allocation routines. Fixes: eea85914d15b ("drm/amdgpu: save ring content before resetting the device") Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add new sources for DCN6Aurabindo Pillai107-1/+48882
Add DCN6 code to DC, DML2, and DMUB Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06Merge tag 'kvm-s390-master-7.2-3' of ↵Paolo Bonzini16-118/+320
https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD KVM: s390: Misc fixes for 7.2 Fix a bunch of small issues that came up during the previous round of fixes. They are mostly extremely unlikely races, but they should be fixed nonetheless.
2026-08-06KVM: SVM: make svm_flush_tlb_gva do a full asid flush if NPT enabledPaolo Bonzini7-15/+29
Red Hat is seeing multiple reports of Windows memory corruptions (and consequent BSODs) with hv-tlbflush=on, on AMD processors only. The crashes, while extremely rare, happen even with a stock configuration, but with Driver Verifier enabled they can be detected after approximately 200 VM hours. In particular, Alexander Lougovski measured the following: - on AMD Turin, 15 crashes in 3300 VM hours - on AMD Milan, 2 crashes in 500 VM hours (there are fewer hours here due to the host being smaller) - on Intel Sapphire Rapids, 0 crashes in 8000 VM hours - on AMD Turin with full TLB flush (not exactly this patch but similar), no crashes in ~2 weeks of run time which should also be ~7000 VM hours For Turin, the microcode version was 0x0b002162, which (assuming this is the same issue) should not be affected by the problem listed in https://knowledge.broadcom.com/external/article/419026/bsod-on-virtual-machines-running-on-amd.html; on the other hand that problem should not apply to earlier processors. AMD has not provided any information or analysis yet, and when we asked we didn't know yet that it reproduced on Milan as well. As to the workload, Alexander threw more or less everything at the same time at the VM: - a full Windows Defender scan every 30 minutes - a disk I/O job - a loop doing repeated mmap of system files (mostly to hope that it triggers some consistency check in the Windows memory manager) - SQL Express 2022 + StressDB (1.6M rows), with the host doing queries (75% write/25% read) via sqlcmd Driver Verifier is able to detect BSODs more or less at the same time as the pages are freed. They mostly happen in the Windows Defender filter driver, but occasionally also in the networking stack (e.g., afd.sys) or elsewhere in the filesystem stack (e.g., fltmgr.sys). The flush is issued from kvm_hv_vcpu_flush_tlb(), which receives the cross-CPU requests from the Hyper-V TLB flush hypercalls via a kfifo and is invoked by the KVM_REQ_HV_TLB_FLUSH request. The mechanism is the same for both Intel and AMD, and the handler for both vendors is a simple INVVPID(ADDR)/INVLPGA instruction. Because the request is handled on the destination CPU, there is a question of what happens if the VM is migrated across physical CPUs. In that case, the INVLPGA instruction would use a stale svm->vmcb->control.asid; but if anything that might do an *unnecessary* flush (on an asid that's being used for another VM) and then pre_svm_run() would force a full TLB rebuild. So, for lack of better ideas, this patch forces a full ASID bump in svm_flush_tlb_gva(). To avoid paying the price on Intel and also to avoid unnecessary loops on AMD, the flush_tlb_gva op now returns whether it did a full flush or not; kvm_hv_vcpu_flush_tlb() takes note and exits its loops immediately. While there is an obvious performance impact, about half of the benefit from Hyper-V tlbflush is preserved (10% vs. 20% on the SQL Server workload). kvm_mmu_invalidate_addr() is the only other caller of the flush_tlb_gva op. The change would have a performance impact on every intercepted INVLPG and, for nested SVM, on every L1 INVLPGA. For INVLPGA specifically, this covers the same suspected issue but for nested hypervisors, so it is correct to apply the workaround; for INVLPG on shadow paging, instead, the impact would be stronger and, due to lack of data, for now the use of INVLPGA is left in place in svm_flush_tlb_gva(). Analyzed-by: Vitaly Kuznetsov <vkuznets@redhat.com> Analyzed-by: Alexander Lougovski <alougovs@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-08-06Merge branch 'bpf-track-overlapping-rcu-protection'Kumar Kartikeya Dwivedi6-6/+220
Ning Ding says: ==================== bpf: Track overlapping RCU protection Preemption-disabled and IRQ-disabled regions provide RCU protection, but the verifier does not account for them. Current implementation can invalidate a task kptr while another RCU source remains active, or keep it valid after the final source ends. Track these regions and invalidate RCU-protected pointers only after the last protection ends. Add task kptr tests for overlapping protection and final-exit rejection. This follows review of the applied spin-unlock fix series [1]. Tested in QEMU/KVM: ./test_progs -t task_kfunc ./test_progs -t preempt_lock ./test_progs -t irq [1] https://lore.kernel.org/r/20260803112615.3362122-1-dingning04@gmail.com ==================== Link: https://patch.msgid.link/20260805233940.3966981-1-dingning04@gmail.com Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
2026-08-06selftests/bpf: Test overlapping RCU protectionNing Ding4-0/+204
Add task kptr tests that keep RCU protection active after a spin or RCU unlock when preemption or IRQs remain disabled. Also test the reverse order with explicit RCU. Verify that task kptrs are rejected after leaving the final preemption-disabled or IRQ-disabled region. Signed-off-by: Ning Ding <dingning04@gmail.com> Link: https://lore.kernel.org/bpf/20260805233940.3966981-3-dingning04@gmail.com Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
2026-08-06bpf: Account for preempt and IRQ state in RCU protectionNing Ding2-6/+16
Disabling preemption or local IRQs keeps the current CPU in an RCU read-side critical section, but in_rcu_cs() does not account for either state. The verifier therefore rejects safe kptr accesses and invalidates pointers when another RCU source ends. Include preemption-disabled and IRQ-disabled state in in_rcu_cs(). Invalidate RCU-protected pointers on RCU unlock, preempt enable, or IRQ restore only after the final protection ends. Signed-off-by: Ning Ding <dingning04@gmail.com> Link: https://lore.kernel.org/bpf/20260805233940.3966981-2-dingning04@gmail.com [ kkd: Simplify was_in_rcu_cs on spin unlock and adjust the selftest. ] Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
2026-08-06drm/amd: Add DCN6 register headersAurabindo Pillai6-0/+74491
Add new headers for: - dcn 6.0.0 - dpcs 6.0.0 - mmhub 5.0.1 Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: reject oversized IBs with per-ring packet limitsCandice Li1-1/+26
On GFX rings, amdgpu_cs_p2_ib() passed user-supplied ib_bytes through to ib->length_dw without a limit, while ring_emit_ib() encodes length into packet fields. Oversized values can corrupt adjacent control bits and destabilize command submission. Add a per-ring IB packet size limit helper and reject command submissions exceeding the corresponding dword limit before IB allocation. Use the documented 20-bit limit for GFX/compute/SDMA/VPE, and apply the MM fallback limit for other ring types. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/userq: serialize queue map against GPU resetJesse Zhang1-0/+5
Creating a user queue can race with a GPU reset. While recovery holds reset_domain->sem for write, MES is unresponsive, so the ADD_QUEUE from amdgpu_userq_map_helper() times out (-110) and an otherwise valid queue create fails: amdgpu: MES(0) failed to respond to msg=ADD_QUEUE [drm:mes_userq_map [amdgpu]] *ERROR* Failed to map queue in HW, err (-110) amdgpu: [drm] *ERROR* ... Failed to map Queue amdgpu: [drm] *ERROR* ... Failed to create usermode queue Take reset_domain->sem for read around the map so it runs only once MES is back up. This mirrors amdgpu_userq_cleanup() and honors the userq_mutex -> reset_domain->sem order; the reset path never takes userq_mutex, so there is no deadlock. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06dt-bindings: leds: backlight: Convert TPS65217 to DT schemaEduard Bostina3-105/+170
Convert the Texas Instruments TPS65217 bindings to DT schema. During the conversion, the following updates were made: - Documented the 'regulators', 'charger' and 'pwrbutton' child nodes, which are used by the boards but were missing from the old txt binding. - Documented the 'interrupts', 'interrupt-controller', '#interrupt-cells' and 'ti,pmic-shutdown-controller' properties, which are used by the am335x boards and read by the driver. The regulator/tps65217.txt binding documented the same 'ti,tps65217' compatible and is superseded by this schema, so remove it as well. Signed-off-by: Eduard Bostina <egbostina@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260723100605.628882-5-egbostina@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06drm/amdgpu/userq: mark a queue unmapped after a per-queue resetJesse Zhang1-1/+11
mes_userq_reset() unmaps the queue via the low-level mes_userq_unmap() (REMOVE_QUEUE) but does not update queue->state, so the queue still looks MAPPED. The destroy path then issues a second, redundant REMOVE_QUEUE for the already-removed queue; for gfx that unmap waits on an EOP that never arrives, times out (-110) and escalates to a full GPU reset. Mark the queue UNMAPPED on a successful reset-path unmap so destroy skips the redundant REMOVE_QUEUE. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: recover user queues in the shared priv-fault helperJesse Zhang1-3/+17
If a priv/bad-op fault does not match a kernel queue slot, it belongs to a MES-scheduled user queue. Extend the shared amdgpu_gfx_handle_priv_fault() helper introduced by commit d8ab7636160e ("drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12") to recover it: gate on adev->gfx.disable_uq, reset a compute user queue directly from its doorbell, and for a gfx user queue (whose IV carries no doorbell) record the HW slot and schedule the per-IP recovery worker. v2: - gate on adev->gfx.disable_uq instead of !adev->enable_mes (Alex) - document why both the doorbell (compute) and HW-slot (gfx) reset paths are needed (Alex) v3: - rebase amd-staging-drm-next. adapt to the commit 9243cf4777fc ("drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12"); no functional change Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Mario Sopena-Novales <Mario.Novales@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gfx12: add priv-fault user-queue recovery workerJesse Zhang1-0/+39
Mirror the gfx11 priv-fault user-queue recovery worker for GFX12, reading the doorbell back from the HQD via soc24_grbm_select. The shared amdgpu_gfx_handle_priv_fault() helper schedules this worker for a gfx user-queue fault; wiring the helper up is done in a later patch. v2: - gate on adev->gfx.disable_uq instead of !adev->enable_mes (Alex) - document why both the doorbell (compute) and HW-slot (gfx) reset paths are needed (Alex) v3: - rebase amd-staging-drm-next. adapt to the commit 9243cf4777fc ("drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12"); no functional change Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Mario Sopena-Novales <Mario.Novales@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gfx11: add priv-fault user-queue recovery workerJesse Zhang1-0/+39
A gfx user-queue priv/bad-op fault is raised by the ME and carries only the HW slot, not the faulting queue's doorbell. Add a per-IP worker that drains adev->gfx.userq_priv_fault_slots, reads the doorbell back from each HQD via soc21_grbm_select (regCP_RB_DOORBELL_CONTROL), looks up the user queue and kicks its per-queue reset. The shared amdgpu_gfx_handle_priv_fault() helper schedules this worker for a gfx user-queue fault; wiring the helper up is done in a later patch. v2: - gate on adev->gfx.disable_uq instead of !adev->enable_mes (Alex) - document why both the doorbell (compute) and HW-slot (gfx) reset paths are needed (Alex) v3: - rebase amd-staging-drm-next. adapt to the commit 9243cf4777fc ("drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12"); no functional change Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Mario Sopena-Novales <Mario.Novales@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: track faulted gfx user-queue slotsJesse Zhang1-0/+3
A gfx priv/bad-op fault IV carries only the HW slot (ring_id), not the faulting user queue's doorbell. Add userq_priv_fault_slots (an atomic bitmap of faulted slots, so concurrent faults are not dropped) and userq_priv_fault_work to struct amdgpu_gfx; a worker drains the bitmap and reads the doorbell back from each HQD to locate and reset the queue. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06mfd: macsmc: Fix key count endianness annotationSven Peter1-3/+5
SMC firmware returns the value of the #KEY key in big-endian unlike most other keys. Reading it through apple_smc_read_u32() into a plain u32 and then converting with be32_to_cpu() makes sparse complain: drivers/mfd/macsmc.c:462:26: sparse: cast to restricted __be32 Read the raw value into a __be32 using apple_smc_read() instead. Fixes: e038d985c982 ("mfd: Add Apple Silicon System Management Controller") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202607181046.OANjIoqR-lkp@intel.com/ Signed-off-by: Sven Peter <sven@kernel.org> Reviewed-by: Janne Grunau <j@jannau.net> Reviewed-by: Joshua Peisach <jpeisach@ubuntu.com> Link: https://patch.msgid.link/20260719-b4-macsmc-be32-fix-v1-1-c7b1936307fa@kernel.org Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06drm/amdgpu: Fix lockdep false positive in amdgpu_lockdep_initVitaly Prosyak1-6/+15
Move fs_reclaim_acquire() to before all lock acquisitions to eliminate false positive circular locking dependency warning. This is a 7.2-cycle regression fix suitable for stable backport. v3: Address Mikhail Gavrilov technical review: - Clarify that fs_reclaim_acquire/release pair only REGISTERS the fs_reclaim lock class, does NOT create a static edge when called with no locks held - Explain that the actual fs_reclaim -> notifier_lock edge is established at runtime during memory reclaim -> MMU notifier path - Add Cc: Arunpravin PaneerSelvam v2: Address Mikhail Gavrilov review feedback: - Fix author name: Michael -> Mikhail Gavrilov in all trailers - Add Fixes: tag to link regression to original commit - Add Tested-by: Mikhail Gavrilov (tested on RX 7900 XTX) Fixes: 1d0f5838b126 ("drm/amdgpu: Add lockdep annotations for lock ordering validation") Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Analyzed-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Test-case-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Suggested-by: Christian König <christian.koenig@amd.com> Tested-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Arunpravin PaneerSelvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: use find_clk_level() for DPM level markingPriya Hosur1-7/+22
Replace the simple exact-match loop in emit_clk_levels with a call to smu_v14_0_0_find_clk_level() introduced in patch 1. The helper already handles both exact and closest-match semantics. Build a stack-local frequency table from the DPM levels (using reverse index for SMU_MCLK since MemPstateTable stores levels high-to-low), then call the helper once to find the active level. The SMU reports time-filtered average frequencies that often do not match any DPM table entry exactly. Without closest-match fallback, MCLK, FCLK and other clocks show DPM levels but never display the * marker, breaking userspace tools that rely on it to identify the active frequency. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: add SMU_DCEFCLK support in DPM frequency queriesPriya Hosur1-0/+28
Add SMU_DCEFCLK case to smu_v14_0_1_get_dpm_freq_by_index and smu_v14_0_0_get_dpm_freq_by_index using DcfClocks[] with NumDcfClkLevelsEnabled bounds check. Add matching case in both get_dpm_level_count functions. Add SMU_DCEFCLK case in emit_clk_levels to list DCEF DPM levels. No * marker is emitted since SmuMetrics_t has no DcfclkFrequency field (same firmware limitation as Phoenix). Without this, pp_dpm_dcefclk reports N/A on Strix Halo. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: add IP_VERSION(11,5,1) to vclk/dclk DPM sysfs whitelistsPriya Hosur1-2/+6
Add IP_VERSION(11,5,1) to pp_dpm_vclk and pp_dpm_dclk visibility whitelists so these sysfs entries are exposed on Strix Halo (GC 11.5.1). Add IP_VERSION(11,5,1) to pp_dpm_vclk1 and pp_dpm_dclk1 whitelists with the existing num_vcn_inst >= 2 guard since Strix Halo has two VCN instances. Without this, amd-smi reports N/A for VCLK0, VCLK1, DCLK0 and DCLK1 clocks. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: fix DCLK metric reporting via VCLK level indexPriya Hosur1-0/+52
SmuMetrics_t has no DclkFrequency field but DCLK and VCLK have separate DPM clock tables with different frequencies at each level. Introduce smu_v14_0_0_find_clk_level(), a shared helper that finds the closest DPM level for a given target frequency in a frequency array. For METRICS_AVERAGE_DCLK, use the helper to find the DPM level whose VCLK frequency matches the reported VclkFrequency and return the DCLK frequency at that same level index, since both clocks share the same level count (VcnClkLevelsEnabled / Vcn0ClkLevelsEnabled). The original code returned 0 for METRICS_AVERAGE_DCLK, which broke the active-level marker in pp_dpm_dclk entirely. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gmc12.1: implement tlb inv semaphoreAlex Deucher1-0/+46
Needed to properly lock the interface before using it. Cc: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: restore user PPT limits after GPU resetYang Wang1-1/+2
GPU reset reinitializes PMFW and reloads the platform power table. The saved user policy remains valid, but suspend-only restore does not run because adev->in_suspend is clear. Restore the active PPT policy from SMU late initialization while the device is in reset recovery. Route each value through the common range validation and ASIC setter before updating PMFW. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.54.0.dirty) at 2026-09-29 18:24:07 +0000